APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations (1997)
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| Venue: | DSP BLOCK DIAGRAMS INTO EFFICIENT SOFTWARE IMPLEMENTATIONS”, DAES |
| Citations: | 41 - 11 self |
BibTeX
@INPROCEEDINGS{Bhattacharyya97apganand,
author = {Shuvra S. Bhattacharyya and Praveen K. Murthy and Edward A. Lee},
title = {APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations},
booktitle = {DSP BLOCK DIAGRAMS INTO EFFICIENT SOFTWARE IMPLEMENTATIONS”, DAES},
year = {1997},
pages = {33--60},
publisher = {}
}
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Abstract
Dataflow has proven to be an attractive computational model for graphical DSP design environments that support the automatic conversion of hierarchical signal flow diagrams into implementations on programmable processors. The synchronous dataflow (SDF) model is particularly well-suited to dataflowbased graphical programming because its restricted semantics offer strong formal properties and significant compile-time predictability, while capturing the behavior of a large class of important signal processing applications. When synthesizing software for embedded signal processing applications, critical constraints arise due to the limited amounts of memory. In this paper, we propose a solution to the problem of jointly optimizing the code and data size when converting SDF programs into software implementations. We consider two approaches. The first is a customization to acyclic graphs of a bottom-up technique, called pairwise grouping of adjacent nodes (PGAN), that was proposed earlier f...
