Global Trade-off between Code Size and Performance for Loop Unrolling on VLIW Architectures
| Citations: | 2 - 0 self |
BibTeX
@TECHREPORT{Heydemann_globaltrade-off,
author = {K. Heydemann and F. Bodin and P.M.W. Knijnenburg},
title = {Global Trade-off between Code Size and Performance for Loop Unrolling on VLIW Architectures},
institution = {},
year = {}
}
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Abstract
Many media processors [28, 7, 14, 8, 18, 27], used for computing intensive embedded applications, are VLIW architectures that rely on the compiler to exploit Instruction Level Parallelism. Loop unrolling is generally used to expose instruction parallelism but computing the unrolling factor is very difficult as instruction cache misses and spill code can cancel the expected benefit of the transformation. Moreover increasing the code size directly impacts on the embedded system cost. In this paper, we propose a method, called UFC (Unrolling Factor computation under Constraints) to compute unrolling factors of set of loops while taking into account code size, a major issue for embedded systems. Keywords: Loop Unrolling, Iterative compilation, Code optimization, Feedback directed compilation, Instruction level parallelism. 1
