An Analog Neural Network Processor with Programmable Topology (1991)
| Venue: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
| Citations: | 18 - 7 self |
BibTeX
@ARTICLE{Boser91ananalog,
author = {Bernhard E. Boser and Eduard Säckinger and Jane Bromley and Yann LeCun and Lawrence D. Jackel},
title = {An Analog Neural Network Processor with Programmable Topology},
journal = {IEEE JOURNAL OF SOLID-STATE CIRCUITS},
year = {1991},
volume = {26},
number = {12},
pages = {2017--2025}
}
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Abstract
The architecture, implementation, and applications of a special purpose neural network processor are described. The chip performs over 2000 multiplications and additions simultaneously. Its datapath is particularly suitable for the convolutional topologies that are typical in classification networks, but can also be configured for fully connected or feedback topologies. Resources can be multiplexed to permit implementation of networks with several hundreds of thousands of connections on a single chip. Computations are performed with 6 Bits accuracy for the weights and 3 Bits for the neuron states. Analog processing is used internally for reduced power dissipation and higher density, but all input/output is digital to simplify system integration. The practicality of the chip is demonstrated with an implementation of a neural network for optical character recognition. This network contains over 130,000 connections and is evaluated in 1 ms.
