## Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits (1999)

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Venue: | IEEE Trans. CAD |

Citations: | 27 - 5 self |

### BibTeX

@ARTICLE{Shepard99harmony:static,

author = {Kenneth L. Shepard and Vinod Narayanan and Senior Member and Ron Rose},

title = {Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits},

journal = {IEEE Trans. CAD},

year = {1999},

volume = {18},

pages = {1132--1150}

}

### Years of Citing Articles

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### Abstract

As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noise-stability metric is introduced to demonstrate how noise can be analyzed systematically on a full-chip basis using simulationbased transistor-level analysis. We then describe Harmony, a two-level (macro and global) hierarchical implementation of static noise analysis. At the macro level, simplified interconnect models and timing assumptions guide efficient analysis. The global level involves a careful combination of static noise analysis, static timing analysis, and detailed interconnect macromodels based on reduced-order modeling techniques. We describe how the interconnect macromodels are practically employed to perform coupling analysis and how timing constraints can be use...

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S’85–M’91) received the B.S.E. degree from
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1 | S'85-M'91i received the B.S.E. degree from Princeton Llniversity - Prentice-Hall - 1987 |