## Power Reduction by Simultaneous Voltage Scaling and Gate Sizing (2000)

Venue: | in Proc. of ASPDAC’00 |

Citations: | 11 - 4 self |

### BibTeX

@INPROCEEDINGS{Chen00powerreduction,

author = {Chunhong Chen and Majid Sarrafzadeh},

title = {Power Reduction by Simultaneous Voltage Scaling and Gate Sizing},

booktitle = {in Proc. of ASPDAC’00},

year = {2000},

pages = {333--338}

}

### OpenURL

### Abstract

This paper proposes to use voltage-scaling (VS) and gate-sizing (GS) simultaneously for reducing power consumption without violating the timing constraints. We present algorithms for simultaneous VS and GS based on the MaximumWeighted -Independent-Set problem. We describe the slack distribution of circuit, completeness of gate library and discreteness of supply voltage, and discuss their effects on power optimization. Experimental results show that the average power reduction ranges from 23.3% to 56.9% over all tested circuits. I. INTRODUCTION Because of the increased circuit density and speed, the power dissipation has emerged as an important consideration in circuit design. A lot of efforts on power reduction have been made at various levels of design abstraction (such as system, architectural, logic and layout levels). Considering the fact that the charging/discharging of capacitance is the most significant source of power dissipation in well-designed CMOS circuits, most research ...

### Citations

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Citation Context ...tten as ) 4 ( / ) + = i FO i i w w k d t where i c c ks= . Basically, (4) indicates that a larger gate is required for the delay reduction if it drives more fanouts. Furthermore, it has been shown in =-=[14]-=- that the gate delay at supply voltage V dd is approximately proportional to kV dd /(V dd - V ) 2 , where 1 The internal capacitance includes the internal cell wiring, parasitic and internal channel c... |

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17 | An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages
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(Show Context)
Citation Context ...tion and power reduction for circuit 9symml 2 These are average values over all types of gates. 3 In all experimental results, the power consumption includes the power penalty due to level converters =-=[5]-=-. before optimization TABLE I POWER REDUCTION (%) WITH DIFFERENT GATE LIBRARIES (USING V high = 5.0 V AND V low = 3.5 V) Library A Global-completeness: 0.08 Local-completeness: 0.78 Library B Global-c... |

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(Show Context)
Citation Context ...teness of Gate Library The GS is strongly related to the underlying gate library. In order to find the optimal solution using GS, Chen and Sarrafzadeh first proposed the notion of complete library in =-=[10]-=-. A complete library implies that, for each type of gate, there is sufficiently large number of cells available with different size and delay. In real designs, it is impossible and unnecessary to crea... |

11 | et al, “Design methodology of ultra low-power MPEG4 codec core exploiting voltage scalin techniques - Usami - 1998 |

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Citation Context ... fact motivates us to find the best combination or simultaneous application of VS and GS for low power design. More recently, an approach of using GS to create new timing slack for VS was reported in =-=[13]-=-. However, essentially GS and VS were done separately and locally in the algorithm. In this paper, we deal with the problem of reducing power dissipation of a technology-mapped circuit under the timin... |

7 | A gate resizing technique for high reduction - Girard, Landrault, et al. - 1997 |

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Citation Context ...ain. This process repeats until Q r (or Q s ) is empty. It should be pointed out that the MWIS problem is NP-complete on general graphs. It is, however, polynomial-time solvable for transitive graphs =-=[17]-=-. A formal description of the GS algorithm is given below (the VS-algorithm is similar and hence omitted). GS-Algorithm (circuit, timing-constraints, gate library) begin calculate the node delay, slac... |

4 |
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Citation Context ...ore power saving, it is preferable to use supply voltages of high discreteness. V. EXPERIMENT AND DISCUSSION We implemented our algorithms for VS, GS, and simultaneous VS and GS under SIS environment =-=[18]-=-. Experiments were carried out on a set of MCNC benchmark circuits using some combinations of VS and GS: single VS, single GS, VS plus GS, GS plus VS, and simultaneous VS and GS. Before running our al... |

4 | et al., “Automated low power technique exploiting multiple supply voltages applied to a media processor”, Custom Integrated Circuit Conference - Usami - 1997 |

3 | et al, "Automated Low Power Technique Exploiting Multiple Supply Voltage Applied to a Media Processor", Custom Integrated Circuit Conference - Usami - 1997 |

3 | Slack equalization algorithm: precise slack distribution for low-level synthesis
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(Show Context)
Citation Context ...s the timing constraints, we have slack time s(i)s0 for each node i . The problem is how to assign the slacks to nodes/edges such that the initial slacks can be fully exploited for power optimization =-=[15]-=-. A typical approach for the slack assignment is the Zero-Slack-Algorithm [16]. However, the algorithm is not able to take into account the discrete nature of node delay in VS/GS technique. In this se... |

3 |
et al. SIS: a system for sequential circuit synthesis
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(Show Context)
Citation Context ...ore power saving, it is preferable to use supply voltages of high discreteness. V. EXPERIMENT AND DISCUSSION We implemented our algorithms for VS, GS, and simultaneous VS and GS under SIS environment =-=[18]-=-. Experiments were carried out on a set of MCNC benchmark circuits using some combinations of VS and GS: single VS, single GS, VS plus GS, GS plus VS, and simultaneous VS and GS. Before running our al... |

2 |
E.J.Yoffa, "Generation of performance constraints for layout
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(Show Context)
Citation Context ...lem is how to assign the slacks to nodes/edges such that the initial slacks can be fully exploited for power optimization [15]. A typical approach for the slack assignment is the Zero-Slack-Algorithm =-=[16]-=-. However, the algorithm is not able to take into account the discrete nature of node delay in VS/GS technique. In this section, we will describe a basic algorithm for VS and GS. First, we have the fo... |

2 |
E.J.Yoffa, “Generation of performance constraints for layout
- Nair, Berman, et al.
- 1989
(Show Context)
Citation Context ...lem is how to assign the slacks to nodes/edges such that the initial slacks can be fully exploited for power optimization [15]. A typical approach for the slack assignment is the Zero-Slack-Algorithm =-=[16]-=-. However, the algorithm is not able to take into account the discrete nature of node delay in VS/GS technique. In this section, we will describe a basic algorithm for VS and GS. First, we have the fo... |

1 | et al., "Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques - Usami - 1998 |