A Fully Integrated, Low Noise and Low Power BiCMOS Front-end Readout System for Capacitive Detectors
BibTeX
@MISC{Philippe_afully,
author = {Chaoying-Christine Guo Philippe and Philippe Schmitt and Grzegorz Deptuch and Yongcai-yann Hu},
title = {A Fully Integrated, Low Noise and Low Power BiCMOS Front-end Readout System for Capacitive Detectors},
year = {}
}
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Abstract
Bipolar transistors are interesting for low noise front-end readout systems when high speed and low power consumption are required. This paper presents a fully integrated, low noise front-end design for the future Large Hadron Collider (LHC) experiments using the radiation hard SOI BiCMOS process. In the present prototype, the input-referred Equivalent Noise Charge (ENC) of 990 electrons (rms) for 12 pF detector capacitance with a shaping time of 25 ns and power consumption of 1.4 mW/channel has been measured. The gain of this front-end is 90 mV/MIP (Minimum Ionisation Particle: 1 MIP= 3.84 fC) with non-linearity of less than 3% and linear input dynamic range is 5 MIP. These results are obtained at room temperature and before irradiation. The measurements after irradiations by high intensity pion beam with an integrated flux of 1.0 10 14 pions/cm 2 are also presented in this paper.
