Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which re-use the configurable hardware during program execution.
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281
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Garp: A MIPS Processor with a Reconfigurable Coprocessor
– Hauser, Wawrzynek
- 1997
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207
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Field-Programmable Gate Arrays
– Brown, Francis, et al.
- 1992
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175
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VPR: A New Packing, Placement and Routing Tool for FPGA Research
– Betz, Rose
- 1997
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153
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A high-performance microarchitecture withv hardware-programmable functional units
– Razdan, Smith
- 1994
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130
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The Chimaera reconfigurable functional unit
– Hauck, Fry, et al.
- 1997
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106
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Wirthlin “A Dynamic Instruction Set Computer
– Hutchings, J
- 1995
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93
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A Time-Multiplexed FPGA
– Trimberger
- 1997
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92
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The roles of FPGAs in reprogrammable systems
– Hauck
- 1998
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89
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Architecture of field programmable gate arrays,” Proc
– Rose, Sangiovanni-Vincentelli
- 1993
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88
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JHDL - an HDL for reconfigurable systems
– Bellows, Hutchings
- 1998
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81
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Splash 2
– Arnold, Buell, et al.
- 1992
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74
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Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators
– Babb, Tessier, et al.
- 1993
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70
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PipeRench: A Reconfigurable Architecture and Compiler
– Goldstein, Schmit, et al.
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66
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VLSI Cell Placement Techniques
– Shahookar, Masunder
- 1991
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66
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An efficient logic emulation system
– Varghese, Butts, et al.
- 1993
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63
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The Transmogrifier C hardware description language and compiler for FPGAs
– Galloway
- 1995
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62
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NAPA C: Compiling for hybrid RISC/FPGA architectures
– Gokhale, Stone
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59
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The Garp architecture and C compiler
– Callahan, Hauser, et al.
- 2000
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58
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A Detailed Router for Field-Programmable Gate Arrays
– Brown, Rose, et al.
- 1992
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58
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Reconfigurable Pipelined Datapaths
– Cronquist
- 1999
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55
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The design and implementation of a context switching FPGA
– Scalera, Vázquez
- 1998
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42
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New performance-driven FPGA routing algorithms
– ALEXANDER, ROBINS
- 1995
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41
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Parallelizing applications into silicon
– Babb, Rinard, et al.
- 1999
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41
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Configuration pre-fetch for single context reconfigurable processors
– Hauck
- 1998
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40
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Specifying and Compiling Applications for RaPiD
– Cronquist, Franklin, et al.
- 1998
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39
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Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why you don’t really want
– DeHon
- 1999
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38
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Fast module mapping and placement for datapaths in FPGAs
– Callahan, Chong, et al.
- 1998
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38
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Improving Functional Density Through Run-Time Constant Propagation
– Wirthlin, Hutchings
- 1997
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37
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DPGA Utilization and Application
– DeHon
- 1996
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37
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Compilation tools for run-time reconfigurable designs
– Luk, Shirazi, et al.
- 1997
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37
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PAM-Blox: High Performance FPGA Design for Adaptive Computing
– Mencer, Morf, et al.
- 1998
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36
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A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
– Miyamori, Olukotun
- 1998
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36
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FPGA Routing and Routability Estimation Via Boolean
– Wood, Rutenbar
- 1997
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36
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Accelerating Boolean Satisfiability with Configurable Hardware
– Zhong, Martonosi, et al.
- 1998
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35
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FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and
– Betz, Rose
- 1999
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35
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A CAD Suite for High-Performance FPGA Design
– Hutchings, Bellows, et al.
- 1999
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35
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A Fast Routability-Driven Router for FPGAs
– Swartz, Betz, et al.
- 1998
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33
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Managing Pipeline-Reconfigurable FPGAs
– Cadambi, Weener, et al.
- 1998
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32
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Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution
– Cong, Wu, et al.
- 1999
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32
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ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator
– Kastrup, Bink, et al.
- 1999
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31
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The design of an SRAM-based field-programmable gate array --- part II: Circuit design and layout
– Chow, Seo, et al.
- 1999
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31
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Configuration compression for the Xilinx XC6200 FPGA
– Hauck, Li, et al.
- 1999
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30
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A simulation tool for dynamically reconfigurable field programmable gate arrays
– Lysaght, Stockwood
- 1996
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29
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Sequencing run–time reconfigured hardware with software
– Hutchings
- 1996
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28
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Trading quality for compile time: ultra-fast placement for FPGAs
– Sankar, Rose
- 1999
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27
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Fast Compilation for Pipelined Reconfigurable Fabrics
– Budiu, Goldstein
- 1999
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27
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Scheduling designs into a time-multiplexed FPGA
– Trimberger
- 1998
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27
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Pipeline Vectorization for Reconfigurable Systems
– Weinhardt, Luk
- 1999
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25
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Temporal partitioning and scheduling data flow graphs for reconfigurable computers
– Purna, Bhatia
- 1999
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25
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Automating Production of Run-Time Reconfigurable Designs
– Shirazi, Luk, et al.
- 1998
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