## An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs (1997)

### Cached

### Download Links

- [ftp.cs.ucla.edu]
- [cadlab.cs.ucla.edu]
- [cadlab.cs.ucla.edu]
- [ballade.cs.ucla.edu]
- DBLP

### Other Repositories/Bibliography

Venue: | in Proc. Int. Symp. on Physical Design |

Citations: | 7 - 2 self |

### BibTeX

@INPROCEEDINGS{Cong97anefficient,

author = {Jason Cong and Lei He},

title = {An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs},

booktitle = {in Proc. Int. Symp. on Physical Design},

year = {1997},

pages = {45--51}

}

### OpenURL

### Abstract

In this paper, we formulated a new class of optimization problem, named the general CH-posynomial program, which is more general than the simple and bounded-variation CH-posynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the local refinement (LR) operation can be used to optimize the simple, bounded-variation and general CH-posynomial programs. We applied the LR-based optimization algorithm to solve the device sizing problem using accurate table-based model, and the wire sizing and spacing problem with consideration of coupling between multiple nets. Both problems are solved in the context of simultaneous device and wire sizing optimization for deep submicron designs. Experiments show that our LR-based optimization algorithm is very effective and extremely efficient. Up to 16.5% delay reduction is observed when compared with previous work based on the simple device model [1], and up to 31% delay reduction and 100x speedup is observed when compared the global interconnect sizing and spacing work [2]. We believe that our general CH-posynomial formulation and LR-based algorithm can also be applied to other optimization problems in the CAD field.

### Citations

195 | M.A.Horowitz ”Signal delay in RC tree networks
- Rubinstein
- 1983
(Show Context)
Citation Context ...nsistor, containing both transistors and wires. The delay of a stage P (N s ; N t ) where N s is its source and N t is its sink can be written as Eqn. (2) according to the Elmore delay formulation in =-=[27]-=-. t(P (N s ; N t ); X) = X i;j r 0 (i) \Delta f st 0 (i; j) \Delta x j x i + X i;j r 0 (i) \Delta f st 1 (i; j) \Delta 1 x i + X i r 0 (i) \Delta g st (i) \Delta 1 x i + X i r 0 (i) \Delta h st 0 (i) ... |

181 |
TILOS: A posynomial programming approach to transistor sizing
- Fishburn, Dunlop
- 1985
(Show Context)
Citation Context ...e device and interconnect separately. The device sizing problem includes both transistor and gate sizing formulations. The transistor sizing assigns the optimal size for each transistor independently =-=[5, 6]-=-. The gate sizing determines the optimal size for a gate [7, 8, 9]. The interconnect sizing problem, also called the wiresizing problem, was first introduced in [10, 11] to determine the optimal width... |

161 |
Fastcap: a multipole accelerated 3-d capacitance extraction program
- Nabors, White
- 1991
(Show Context)
Citation Context ...ns. We generated area capacitance (c a ), fringe capacitance (c f ) and coupling capacitance (c x ) for a wire in our 0:18m technology with three different widths and spacings via a 3D solver FastCap =-=[23]-=-. As one can see in Table 2, when wires are placed closer and the wire aspect ratio increases in DSM designs, c x between neighboring wires can be 83% of the total wire capacitance. Therefore, it is n... |

111 | Optimal wire sizing and buffer insertion for low power and a generalized delay model
- Lillis, Cheng, et al.
- 1996
(Show Context)
Citation Context ...orithms were proposed in [12, 13, 14, 15, 16]. Recently, several studies consider the simultaneous device and interconnect sizing problem. The simultaneous gate and wire sizing formulation is used in =-=[17, 18, 19, 20]-=-, whereas the simultaneous transistor and interconnect sizing (STIS) formulation is used in [1]. size = 100x n-transistor p-transistor c l / t t 0.05ns 0.1ns 0.2ns 0.3ns 0.05ns 0.1ns 0.2ns 0.3ns 0.225... |

105 | Performance optimization of VLSI interconnect layout”, Integration 21
- Cong, He, et al.
- 1996
(Show Context)
Citation Context ...DSM) designs [3]. Many optimization techniques have been proposed to reduce interconnect delay, including interconnect topology optimization, buffer insertion, and device and interconnect sizing (see =-=[4]-=- for a comprehensive survey). As part of our effort to develop a unified methodology and platform for interconnect optimization, we study the simultaneous device and interconnect sizing problem in the... |

100 | An exact solution of the transistor sizing problem for CMOS circuits using convex optimization
- Sapatnekar, Rao, et al.
- 1993
(Show Context)
Citation Context ...e device and interconnect separately. The device sizing problem includes both transistor and gate sizing formulations. The transistor sizing assigns the optimal size for each transistor independently =-=[5, 6]-=-. The gate sizing determines the optimal size for a gate [7, 8, 9]. The interconnect sizing problem, also called the wiresizing problem, was first introduced in [10, 11] to determine the optimal width... |

71 | Interconnect design for deep submicron ICs
- Cong, He, et al.
- 1997
(Show Context)
Citation Context ...and Intel Corporation under the California MICRO program. 1 1 Introduction The interconnect delay has become the dominant factor in determining the circuit performance in deep submicrons(DSM) designs =-=[3]-=-. Many optimization techniques have been proposed to reduce interconnect delay, including interconnect topology optimization, buffer insertion, and device and interconnect sizing (see [4] for a compre... |

68 | Performance-driven interconnect design based on distributed rc delay model
- Cong, Leung, et al.
- 1993
(Show Context)
Citation Context ...or each transistor independently [5, 6]. The gate sizing determines the optimal size for a gate [7, 8, 9]. The interconnect sizing problem, also called the wiresizing problem, was first introduced in =-=[10, 11]-=- to determine the optimal width for each wire segment in interconnects and polynomial-time optimal algorithms were developed. Later on, alternative wiresizing algorithms were proposed in [12, 13, 14, ... |

55 | Optimal wiresizing under the distributed Elmore delay model
- Cong, Leung
- 1993
(Show Context)
Citation Context ...or each transistor independently [5, 6]. The gate sizing determines the optimal size for a gate [7, 8, 9]. The interconnect sizing problem, also called the wiresizing problem, was first introduced in =-=[10, 11]-=- to determine the optimal width for each wire segment in interconnects and polynomial-time optimal algorithms were developed. Later on, alternative wiresizing algorithms were proposed in [12, 13, 14, ... |

52 | Simultaneous driver and wire sizing for performance and power optimization
- Cong, Koh
- 1994
(Show Context)
Citation Context ...orithms were proposed in [12, 13, 14, 15, 16]. Recently, several studies consider the simultaneous device and interconnect sizing problem. The simultaneous gate and wire sizing formulation is used in =-=[17, 18, 19, 20]-=-, whereas the simultaneous transistor and interconnect sizing (STIS) formulation is used in [1]. size = 100x n-transistor p-transistor c l / t t 0.05ns 0.1ns 0.2ns 0.3ns 0.05ns 0.1ns 0.2ns 0.3ns 0.225... |

48 | RC interconnect optimization under the Elmore delay model
- Sapatnekar
- 1994
(Show Context)
Citation Context ...d in [10, 11] to determine the optimal width for each wire segment in interconnects and polynomial-time optimal algorithms were developed. Later on, alternative wiresizing algorithms were proposed in =-=[12, 13, 14, 15, 16]-=-. Recently, several studies consider the simultaneous device and interconnect sizing problem. The simultaneous gate and wire sizing formulation is used in [17, 18, 19, 20], whereas the simultaneous tr... |

43 |
Geometric programming: methods, computations and applications
- Ecker
- 1980
(Show Context)
Citation Context ...coefficients a pi (X) and b qj (X) are constants. Since exponents in the simple CH-posynomial must be natural numbers, the class of the simple CH-posynomial is a subset of the class of the posynomial =-=[26]-=-. Moreover, the bounded-variation CH-posynomial is defined: Definition 2 (Bounded-Variation CH-posynomial) Eqn. (1) is a bounded-variation CH-posynomial if coefficients satisfy the following condition... |

41 | Optimal Wiresizing for Interconnects with Multiple Sources
- Cong, He
(Show Context)
Citation Context ...d in [10, 11] to determine the optimal width for each wire segment in interconnects and polynomial-time optimal algorithms were developed. Later on, alternative wiresizing algorithms were proposed in =-=[12, 13, 14, 15, 16]-=-. Recently, several studies consider the simultaneous device and interconnect sizing problem. The simultaneous gate and wire sizing formulation is used in [17, 18, 19, 20], whereas the simultaneous tr... |

38 | Interconnect sizing and spacing with consideration of coupling capacitance
- Cong, He, et al.
- 2001
(Show Context)
Citation Context ...nt E i , even through c a (i); c f (i) and c x (i) are functions of width and edge-to-edge space of E i in our 2D capacitance model. We consider two wire sizing and spacing formulations introduced in =-=[2]-=-. One is the symmetric wire sizing formulation, where wires are always symmetric with respect to initial central-lines as illustrated in Figure 1(a). In contrast, the other is the asymmetric wire sizi... |

35 | A sequential quadratic programming approach to concurrent gate and wire sizing
- Menezes, Baldick, et al.
- 1995
(Show Context)
Citation Context ...orithms were proposed in [12, 13, 14, 15, 16]. Recently, several studies consider the simultaneous device and interconnect sizing problem. The simultaneous gate and wire sizing formulation is used in =-=[17, 18, 19, 20]-=-, whereas the simultaneous transistor and interconnect sizing (STIS) formulation is used in [1]. size = 100x n-transistor p-transistor c l / t t 0.05ns 0.1ns 0.2ns 0.3ns 0.05ns 0.1ns 0.2ns 0.3ns 0.225... |

33 |
Gate sizing in MOS digital circuits with linear programming
- Berkelaar, Jess
- 1990
(Show Context)
Citation Context ... includes both transistor and gate sizing formulations. The transistor sizing assigns the optimal size for each transistor independently [5, 6]. The gate sizing determines the optimal size for a gate =-=[7, 8, 9]-=-. The interconnect sizing problem, also called the wiresizing problem, was first introduced in [10, 11] to determine the optimal width for each wire segment in interconnects and polynomial-time optima... |

29 |
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
- Chen, Chang, et al.
- 1996
(Show Context)
Citation Context ...d in [10, 11] to determine the optimal width for each wire segment in interconnects and polynomial-time optimal algorithms were developed. Later on, alternative wiresizing algorithms were proposed in =-=[12, 13, 14, 15, 16]-=-. Recently, several studies consider the simultaneous device and interconnect sizing problem. The simultaneous gate and wire sizing formulation is used in [17, 18, 19, 20], whereas the simultaneous tr... |

28 | Gamal, Optimal wire and transistor sizing for circuits with non-tree topology - Vandenberghe, Boyd, et al. - 1997 |

21 | Analysis and justification of a simple, practical 2 1/2-d capacitance extraction methodology
- Cong, He, et al.
- 1997
(Show Context)
Citation Context ...under this capacitance model and using the WSS formulaiton. 3.3.1 Capacitance model and WSS formulation A table-based 2.5D capacitance model suitable for layout optimization was presented recently in =-=[28]-=-. The interconnect capacitance comprises the following components: area and fringe capacitances, coupling capacitance, and cross-over and cross-under capacitances. We consider only area, fringe and co... |

19 | Optimal wire sizing and buer insertion for low power and a generalized delay model - Lillis, Cheng, et al. - 1995 |

17 | Post routing performance optimization via multi-link insertion and non-uniform wiresizing
- Xue, Kuh
- 1995
(Show Context)
Citation Context |

16 | An e cient approach to simultaneous transistor and interconnect sizing
- Cong, He
- 1996
(Show Context)
Citation Context ...stract In this paper, we formulated a new class of optimization problem, named the general CH-posynomial program, which is more general than the simple and bounded-variation CH-posynomial programs in =-=[1]-=-. We revealed the general dominance property so that an efficient and unified algorithm based on the local refinement (LR) operation can be used to optimize the simple, bounded-variation and general C... |

16 | Timing and Area Optimization for Standard-Cell VLSI Circuit Design
- Chuang, Sapatnekar, et al.
- 1995
(Show Context)
Citation Context ... includes both transistor and gate sizing formulations. The transistor sizing assigns the optimal size for each transistor independently [5, 6]. The gate sizing determines the optimal size for a gate =-=[7, 8, 9]-=-. The interconnect sizing problem, also called the wiresizing problem, was first introduced in [10, 11] to determine the optimal width for each wire segment in interconnects and polynomial-time optima... |

13 | A New Approach to Simultaneous Buffer Insertion and
- Chu, Wong
- 1997
(Show Context)
Citation Context |

12 |
Switch-Level Delay Models for Digital MOS VLSI
- Ousterhout
- 1984
(Show Context)
Citation Context ...ds are used for measuring. As one can see, r 0 is clearly a function of size, input transition time and output load. Its value may differ by a factor of 2 (note that a similar observation was made in =-=[22]-=- as well, with smaller variation of effective resistance in the technology generation then). Furthermore, c 0 and c f are no longer sufficient to model a wire capacitance, due to increasing importance... |

11 | Optimization of custom MOS circuits by transistor sizing
- Conn, Coulman, et al.
- 1996
(Show Context)
Citation Context ... gate sizing and wire sizing problem under both simple gate model and a voltage-ramp gate model (a general model). The latter model achieves better results but is 10x slower. The transistor sizing in =-=[24]-=- also considers a general device model based on sensitivity computation exploiting a circuit simulation. Logic patterns are needed since circuit simulation is used. Two very recent works [25, 2] consi... |

10 | Fast performance-driven optimization for bu ered clock trees based on Lagrangian relaxation - Chen, Chang, et al. - 1996 |

7 |
An Iterative Gate Sizing Approach with Accurate Delay Evaluation
- Chen, Onodera, et al.
- 1995
(Show Context)
Citation Context ... includes both transistor and gate sizing formulations. The transistor sizing assigns the optimal size for each transistor independently [5, 6]. The gate sizing determines the optimal size for a gate =-=[7, 8, 9]-=-. The interconnect sizing problem, also called the wiresizing problem, was first introduced in [10, 11] to determine the optimal width for each wire segment in interconnects and polynomial-time optima... |

7 |
Pillage, "RC Interconnect Synthesis --- A Moment Fitting Approach
- Menezes, Pullela, et al.
- 1994
(Show Context)
Citation Context |

7 | Theory and algorithm of local-refinement based optimization with application to device and interconnect sizing
- Cong, He
- 1999
(Show Context)
Citation Context ...he global interconnect sizing and spacing (GISS) problem considering the crosstalk capacitance in Section 4. We conclude the paper in Section 5. Proofs of all theorems are given in a technical report =-=[12]-=-. 2. THEORY OF CH-POSYNOMIAL PROGRAMS 2.1. Review of simple and bounded-variation CHposynomial programs In [6], the CH-posynomial (Cong-He posynomial) is defined as a function of positive vector X = f... |

6 | A new approach to simultaneous buer insertion and wire sizing - Chu, Wong - 1997 |

4 |
A 12.7Mchip/s all-digital BPSK direct sequence spread-spectrum IF transceiver in 1.2m CMOS
- Chien, Yang, et al.
- 1994
(Show Context)
Citation Context ... for two nets. One is a 2cm line with 5 buffers. These buffers are inserted for delay minimization. The other is a buffered tree, which is the dclk net in a spread spectrum IF transceiver chip design =-=[29]-=-. Its total wire length is 41518.2 m, and there are 117 drivers and 37 buffers. The original design is in 1.2 m 2-layer metal SCMOS technology, but in our experiment, we use parameters based on our 0.... |

4 | Analysis and justi cation of a simple, practical 2 1/2-d capacitance extraction methodology - Cong, He, et al. - 1997 |

2 | Theory and algorithm of local re nement based optimization with application to transistor and interconnect sizing," Tech. Rep. 970034 (available at http://cadlab.cs.ucla.edu/ ~helei/publications.html), UCLA CS Dept - Cong, He - 1997 |