An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs

An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs (1997)

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by Jason Cong , Lei He

Venue:	in Proc. Int. Symp. on Physical Design
Citations:	7 - 2 self

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@INPROCEEDINGS{Cong97anefficient,
    author = {Jason Cong and Lei He},
    title = {An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs},
    booktitle = {in Proc. Int. Symp. on Physical Design},
    year = {1997},
    pages = {45--51}
}

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Abstract

In this paper, we formulated a new class of optimization problem, named the general CH-posynomial program, which is more general than the simple and bounded-variation CH-posynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the local refinement (LR) operation can be used to optimize the simple, bounded-variation and general CH-posynomial programs. We applied the LR-based optimization algorithm to solve the device sizing problem using accurate table-based model, and the wire sizing and spacing problem with consideration of coupling between multiple nets. Both problems are solved in the context of simultaneous device and wire sizing optimization for deep submicron designs. Experiments show that our LR-based optimization algorithm is very effective and extremely efficient. Up to 16.5% delay reduction is observed when compared with previous work based on the simple device model [1], and up to 31% delay reduction and 100x speedup is observed when compared the global interconnect sizing and spacing work [2]. We believe that our general CH-posynomial formulation and LR-based algorithm can also be applied to other optimization problems in the CAD field.

Citations

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