## A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance (2001)

Venue: | Proceedings of the IEEE Custom Integrated Circuits Conference |

Citations: | 8 - 2 self |

### BibTeX

@INPROCEEDINGS{Lu01afast,

author = {Yi-Chang Lu and Kaustav Banerjee and Mustafa Celik and Robert W. Dutton},

title = {A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance},

booktitle = {Proceedings of the IEEE Custom Integrated Circuits Conference},

year = {2001},

pages = {241--244},

publisher = {IEEE Fellow}

}

### OpenURL

### Abstract

Accurate icurateb assessment ofon-chi clock lioc i diockb2 wickb2 any a priori knowledge a outthei iei7377b at an early stagei the clock desib process.Thi paperipe oduces aneffici28 approach toesti843 the ounds of on-chi clockwi ei2031b-48 at the veryegi2068 of thedesi7 stages. Wi8 thi ii ormati47 more accurate waveforms along the clock dickb utib networks can e otai60 thus greatly reduci-44980b verall length of desiii157b1 . NTRODUCTION As VL@VxI6O}pwpI evolves, a significant portion of the delay is caused by global interconnects. With higher clocking rate, increasing interconnect lengths, and decreasing rise times, inductance effects are more evident than ever. This is especially true for the clock distribution networks, where the delay and the slope of clock waveforms are critical to overall system performance. In the past, several different approaches have been proposed to extract the inductance values [1][2]. Though there are many techniques to accelerate the speed of the electromagnetic field solvers, they are still impractical to be included in the early design phase. This is because it is nearly impossible to obtain the exact current return paths at the very beginning of the design cycle, which are layout dependent. Hence, precise inductance values cannot be calculated without the details of physical information, such as locations of the clock lines and neighboring wires. To address this problem, a geometry-independent model has been developed, in the first part of the paper, which can estimate the bounds of possible on-chip clock wire inductance values at early design stages. The inductance information computed by the model can be incorporated into the delay/slope calculations to reduce several iterations between physical design (layout) and logic synthesis,...

### Citations

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(Show Context)
Citation Context ... h=0.58um w=4um G=1.64um s=0.5um TABLE II l=1mm h=0.58um w=4um G=1.64um s=1um In order to quantify the impact of inductance on clock signal integrity metrics, the Asymptotic Waveform Evaluation (AWE) =-=[11] t-=-echnique was employed. The wire resistance and wire capacitance were extracted to be 0.065 ohm per square and 0.24 fF/µm, respectively, for a 0.18 µm technology file. The waveforms simulated (in Fig... |

366 |
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(Show Context)
Citation Context ... The clock routing problem is to minimize the delay(D) and skew(S). Where D = max t(Cs , Pi ) and S = max | t(Cs , Pi )-t(Cs , Pj )|. In the past decade, the overall delay was modeled as Elmore delay =-=[3]-=-, which accounted for the delay caused by the RC elements only and provided good estimation. The buffer insertion and wire sizing issues were also based on this Elmore delay model. However, for Deep S... |

108 |
Inductance calculations in a complex integrated circuit environment
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- 1972
(Show Context)
Citation Context ...on networks, where the delay and the slope of clock waveforms are critical to overall system performance. In the past, several different approaches have been proposed to extract the inductance values =-=[1]-=-[2]. Though there are many techniques to accelerate the speed of the electromagnetic field solvers, they are still impractical to be included in the early design phase. This is because it is nearly im... |

52 |
Inductance Calculations: Working Formulas and Tables
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(Show Context)
Citation Context ...clock wires (as per [6]) are smaller than the skin depth even at several GHz, as shown in Table 1. TABLE I Frequency 0.5GHz 1.0GHz 2.0GHz 5.0GHz Skin Depth (Cu metal) 2.96um 2.09um 1.48um 0.93um From =-=[7], the part-=-ial self inductance (L) of a on-chip clock wire segment is given by, µ 0l L ------- ⎛ 2l ----------- ⎞ 0.2235( w + t) 1 = ln + --------------------------------- + -- 2π ⎝w+ t⎠ l 2 where w, t... |

40 | The Elmore Delay as Bound for RC Trees with Generalized Input Signals
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Citation Context ...ves the upper bound at: α 1 = – 1 IV. IMPULSE RESPONSE OF AN RLC CLOCK LINE (23) (24) (25) (26) The Elmore delay, which is the first moment of the impulse response, is an upper bound for the RC del=-=ay [9]-=-. However, as mentioned earlier, it does not include inductance effects. Consequently, the higher order model should be used when routing clock networks. The central moments based on probability theor... |

7 |
Fast-henry: a multiple-accelerated 3d inductance extraction program
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(Show Context)
Citation Context ...networks, where the delay and the slope of clock waveforms are critical to overall system performance. In the past, several different approaches have been proposed to extract the inductance values [1]=-=[2]-=-. Though there are many techniques to accelerate the speed of the electromagnetic field solvers, they are still impractical to be included in the early design phase. This is because it is nearly impos... |

5 |
Transmission Line Synthesis via Constrained Multivariable Optimization
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(Show Context)
Citation Context ...mentioned earlier, it does not include inductance effects. Consequently, the higher order model should be used when routing clock networks. The central moments based on probability theory proposed in =-=[10]-=- can be used as design metrics. The core concepts of central moments are summarized below and the simulation demonstrates the importance of including the inductance values in the delay calculation. Th... |

1 |
A 400MHz S/390
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(Show Context)
Citation Context ...ction of the current flow in those wires, as illustrated in Fig. 1(b). 3) The clock wires lying parallel on the same metal level are less likely to serve as return paths due to large separation. From =-=[4]-=-, there are 580 clock sinks on a 17*17 mm 2 die. Assuming that the pins are uniformly distributed, the nearest distance between each pins would be around 700 microns. Thus it is justified to assume th... |

1 |
On-chip inductance and inductive coupling
- Lin, Chang
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(Show Context)
Citation Context ...d be around 700 microns. Thus it is justified to assume that they are not efficient return paths, as illustrated in Fig. 1(c). 4) The total clock wire inductance can be obtained by the cascade method =-=[5]-=-, as shown in Fig. 1(d). 5) No skin depth effects are considered, because the heights of the global clock wires (as per [6]) are smaller than the skin depth even at several GHz, as shown in Table 1. T... |