Abstract

Accurate icurateb assessment ofon-chi clock lioc i diockb2 wickb2 any a priori knowledge a outthei iei7377b at an early stagei the clock desib process.Thi paperipe oduces aneffici28 approach toesti843 the ounds of on-chi clockwi ei2031b-48 at the veryegi2068 of thedesi7 stages. Wi8 thi ii ormati47 more accurate waveforms along the clock dickb utib networks can e otai60 thus greatly reduci-44980b verall length of desiii157b1 . NTRODUCTION As VL@VxI6O}pwpI evolves, a significant portion of the delay is caused by global interconnects. With higher clocking rate, increasing interconnect lengths, and decreasing rise times, inductance effects are more evident than ever. This is especially true for the clock distribution networks, where the delay and the slope of clock waveforms are critical to overall system performance. In the past, several different approaches have been proposed to extract the inductance values [1][2]. Though there are many techniques to accelerate the speed of the electromagnetic field solvers, they are still impractical to be included in the early design phase. This is because it is nearly impossible to obtain the exact current return paths at the very beginning of the design cycle, which are layout dependent. Hence, precise inductance values cannot be calculated without the details of physical information, such as locations of the clock lines and neighboring wires. To address this problem, a geometry-independent model has been developed, in the first part of the paper, which can estimate the bounds of possible on-chip clock wire inductance values at early design stages. The inductance information computed by the model can be incorporated into the delay/slope calculations to reduce several iterations between physical design (layout) and logic synthesis,...

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