A Methodology for Accurate Performance Evaluation in Architecture Exploration (1999)
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| Venue: | In In Proceedings of the Design Automation Conference (DAC 99 |
| Citations: | 17 - 0 self |
BibTeX
@INPROCEEDINGS{Hadjiyiannis99amethodology,
author = {George Hadjiyiannis and Srinivas Devadas},
title = {A Methodology for Accurate Performance Evaluation in Architecture Exploration},
booktitle = {In In Proceedings of the Design Automation Conference (DAC 99},
year = {1999},
pages = {927--932}
}
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Abstract
We present a system that automatically generates a cycle-accurate and bit-true Instruction Level Simulator (ILS) and a hardware implementation model given a description of a target processor. An ILS can be used to obtain a cycle count for a given program running on the target architecture, while the cycle length, die size, and power consumption can be obtained from the hardware implementation model. These figures allow us to accurately and rapidly evaluate target architectures within an architecture exploration methodology for system-level synthesis.
