Abstract

DSYN generates optimized Digital/Analog Converter (DAC) layouts given a set of specifications including performance constraints, a description of the implementation technology, and a set of design parameters. The generation process consists of a synthesis step followed by a layout step. During synthesis a new constrained optimization method is coupled with combination of circuit simulation and DAC design equations. The layout step uses stretching and tiling operations on a set of primitive cells. Prototypes have been demonstrated for an 8-bit, 100-MS/s specification, driving a 37.5-ohm video load, and a static 10-bit specification, driving a 4mA full-scale output current. Both designs use a 5-V supply in a 1.2 m CMOS process. 1 Biographies Robert R. Neff (member) was with the University of California, Berkeley, CA. He is now with Hewlett Packard Company, Palo Alto, CA 94304. Paul R. Gray (fellow) and Alberto Sangiovanni-Vincentelli (fellow) are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 . Coorespondence should be directed to: Dr. Robert Neff Hewlett Packard Company 3500 Deer Creek Road, MS 26U-4 Palo Alto, CA 94304-0867 Phone: (415)857-6220 Fax: (415)857-3637 E-mail: neff@hpl.hp.com 1. This research was supported by the Semiconductor Research Corporation under grant 94-DC-324. 2 I.

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