BibTeX
@MISC{Allani11polynomial-timealgorithms,
author = {Mridula Allani},
title = {Polynomial-Time Algorithms for . . . },
year = {2011}
}
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Abstract
Energy consumption of digital circuits has become a primary constraint in electronic design. The increasing popularity of the portable devices like smart phone, ipad, tablet and notebook has created an overwhelming demand for extended battery life of these devices. Numerous methods for energy reduction in CMOS circuits have been proposed in the literature. Power reduction techniques at various levels of abstraction are used in modern digital designs. Most popular techniques used include power gating, clock gating, multiple-supply voltages, multiple threshold devices. In this work we propose a technique to use dual supply voltages in digital designs in order to get a reduction in energy consumption. Three new algorithms are proposed for finding and assigning low voltage in dual voltage designs. Given a circuit and a supply voltage, the first algorithm finds a suitable value for a lower supply voltage and the other two algorithms assign that lower voltage to individual gates. A linear time algorithm described in the literature is used for computing slacks for all gates in a circuit for a given supply voltage. The slack of a gate is the difference between the critical path delay and the delay
Keyphrases
polynomial-time algorithm supply voltage energy consumption individual gate power reduction technique numerous method primary constraint dual supply voltage popular technique extended battery life digital design multiple threshold device first algorithm suitable value cmos circuit multiple-supply voltage electronic design overwhelming demand linear time algorithm critical path delay modern digital design clock gating low voltage various level energy reduction power gating digital circuit new algorithm dual voltage design smart phone portable device
