An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches

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An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches (2002)

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by Changkyu Kim , Doug Burger , Stephen W. Keckler

Venue:	In International Conference on Architectural Support for Programming Languages and Operating Systems
Citations:	314 - 39 self

BibTeX

@INPROCEEDINGS{Kim02anadaptive,,
    author = {Changkyu Kim and Doug Burger and Stephen W. Keckler},
    title = {An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches},
    booktitle = {In International Conference on Architectural Support for Programming Languages and Operating Systems},
    year = {2002},
    pages = {211--222}
}

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Abstract

Growing wire delays will force substantive changes in the designs of large caches. Traditional cache architectures assume that each level in the cache hierarchy has a single, uniform access time. Increases in on-chip communication delays will make the hit time of large on-chip caches a function of a line's physical location within the cache. Consequently, cache access times will become a continuum of latencies rather than a single discrete latency. This nonuniformity can be exploited to provide faster access to cache lines in the portions of the cache that reside closer to the processor. In this paper, we evaluate a series of cache designs that provides fast hits to multi-megabyte cache memories. We first propose physical designs for these Non-Uniform Cache Architectures (NUCAs). We extend these physical designs with logical policies that allow important data to migrate toward the processor within the same level of the cache. We show that, for multi-megabyte level-two caches, an adaptive, dynamic NUCA design achieves 1.5 times the IPC of a Uniform Cache Architecture of any size, outperforms the best static NUCA scheme by 11%, outperforms the best three-level hierarchywhile using less silicon area-by 13%, and comes within 13 % of an ideal minimal hit latency solution. 1.

Keyphrases

nonuniform cache structure on-chip cache physical design uniform cache architecture hit time multi-megabyte level-two cache multi-megabyte cache memory three-level hierarchywhile dynamic nuca design important data cache hierarchy ideal minimal hit latency solution non-uniform cache architecture on-chip communication delay logical policy traditional cache architecture static nuca scheme physical location single discrete latency substantive change wire delay cache access time cache design uniform access time large on-chip cache large cache

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