## Analog Layout Synthesis- Recent Advances in Topological Approaches

Citations: | 1 - 0 self |

### BibTeX

@MISC{Graeb_analoglayout,

author = {H. Graeb and F. Balasa and R. Castro-lopez and Y. -w. Chang and F. V. Fern and P. -h. Lin and M. Strasser},

title = {Analog Layout Synthesis- Recent Advances in Topological Approaches},

year = {}

}

### OpenURL

### Abstract

Abstract—This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks. I.

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Citation Context ...., [18], [16], [17], [19], [25], instead of bottom-up integration, because the optimal placement of a subcircuit may not lead to the globally optimal placement. Most of them apply simulated annealing =-=[12]-=- based on the topological floorplan representations, such as sequence-pair [22] and B ∗ -tree [5], while the latest one [25] adopts a full deterministic approach which will be introduced in Section IV... |

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