## Timing–Driven Variation–Aware Nonuniform Clock Mesh Synthesis

Citations: | 2 - 2 self |

### BibTeX

@MISC{Abdelhadi_timing–drivenvariation–aware,

author = {Ameer Abdelhadi and Ran Ginosar and Avinoam Kolodny and Eby G. Friedman},

title = {Timing–Driven Variation–Aware Nonuniform Clock Mesh Synthesis},

year = {}

}

### OpenURL

### Abstract

Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. However, these networks incur an increase in dissipated power while consuming significant metal resources. Several methods have been proposed to trade off power and wires to reduce skew. In this paper, an efficient algorithm is presented to reduce skew variations rather than skew, and prioritize the algorithm for critical timing paths, since these paths are more sensitive to skew variations. The algorithm has been implemented for a standard 65 nm cell library using standard EDA tools, and has been tested on several benchmark circuits. As compared to other methods, experimental results show a 37 % average reduction in metal consumption and 39 % average reduction in power dissipation, while insignificantly increasing the maximum skew.

### Citations

1764 |
Computational Geometry: An Introduction
- Preparata, Shamos
- 1985
(Show Context)
Citation Context ...ed from overlapping regions. A run time example of Phase III is shown in Fig. 10. Polygon union and intersection operations can be performed in O(n·log(n)) steps using a segmented tree data structure =-=[20]-=-, where n is the total number of polygon segments. This complexity is the same order as the number of vertices n=O(|G C V |)=O(|S|), and the run-time of this phase is therefore quasi-linear, O(|S|·log... |

38 |
Clock Distribution Networks
- Friedman
- 2001
(Show Context)
Citation Context ...locked elements. These networks achieve low and deterministic skew, low skew variations, and low jitter. Clock meshes also overcome late design changes while satisfying tight time-to-market deadlines =-=[1]-=-. Clock Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commer... |

36 |
Designing the Best Clock Distribution Network
- Restle, Deutsch
- 1998
(Show Context)
Citation Context ...o analyze, optimize, and automate [6],[12],[13]. Routing redundancies require significant resources as compared to optimized tree-based clock distribution networks where point-topoint routing is used =-=[7]-=-. Meshes dissipate higher power [12] due to the large capacitance incurred by the additional metal wires and drivers. Furthermore, clock gating is impractical in most mesh structures. Due to delay dif... |

27 | Reducing clock skew variability via crosslinks
- Rajaram, H, et al.
- 2006
(Show Context)
Citation Context ...zing non-tree distribution networks have been presented, employing either customized meshes [1–7] or automating the process of adding crosslinks to the clock tree to enhance tolerance and lower power =-=[8]-=-,[9]. Yet other papers propose removing some edges from a mesh to reduce power while minimally increasing the skew [10],[11]. While most of these papers focus on skew variations, the approach proposed... |

20 |
The Design and Analysis of the Clock Distribution Network for a 1.2GHz Alpha Microprocessor
- Xanthopoulos
- 2001
(Show Context)
Citation Context ...503-0012-4/10/05...$10.00. meshes constitute an effective alternative for distributing global clock signals, and are used in high performance microprocessors [1] such as the Power4 [2], Digital Alpha =-=[3]-=-, Intel Pentium 4 [4], and Xeon [5]. Nevertheless, non-tree clock distribution networks suffer certain drawbacks. These networks are composed of a large number of mesh nodes and unbalanced loads, maki... |

19 |
Sizing of clock distribution networks for high performance CPU chips
- Desai, Cvijetic, et al.
- 1996
(Show Context)
Citation Context ...hes automate the clock mesh design process. Mesh sizing and, in particular, segment wire width sizing using network flow algorithms have been used to optimize nominal skew rather than skew variations =-=[19]-=-. Other methods start from a clock tree and incrementally add crosslinks among the tree nodes or leaves. Crosslinks are added between those nodes exhibiting high variation. The objective is to add the... |

9 | Combinatorial algorithms for fast clock mesh optimization
- Venkataraman, Feng, et al.
(Show Context)
Citation Context ...aximum skew (ps) Figure 12: Power and maximum skew vs. relative skew tolerance parameter ξ (a) Wire length (um) (c) Maximum skew (ps) (b) Power (mw) Figure 13: Proposed method with ξ = 1 vs. [10] and =-=[11]-=-: (a) wire length, (b) power, and (c) maximum skew relationship among the metal resources, power consumption, and relative skew tolerance parameter ξ. The maximum skew is compared with other methods, ... |

9 | Reduced delay uncertainty in high performance clock distribution networks
- Velenis, Papaefthymiou, et al.
- 2003
(Show Context)
Citation Context ...riations to reduce the effect of skew on timing margins and cycle time. Those clocks that drive a non-critical logic path however must satisfy certain skew variations without affecting the cycle time =-=[16]-=-. By relaxing skew variation requirements in the non-critical paths, power savings can be achieved. The proposed method employs graphtheoretic and geometric algorithms with quasi-linear run time. Usin... |

8 |
Technology scaling impact of variation on clock skew and interconnect delay
- Mehrotra, Boning
- 2001
(Show Context)
Citation Context ...k gating is impractical in most mesh structures. Due to delay differences in the drivers, short-circuit current loops are generated across the redundant mesh paths [12]. Increasing process variations =-=[14]-=-,[15] dissipate more power, since a more tolerant mesh structure dissipates higher power due to greater use of metal and driver oversizing [15]. Several proposals for optimizing non-tree distribution ... |

6 |
Kurd et al., “A Multigigahertz Clocking Scheme for the Pentium® 4 Microprocessor
- A
- 2001
(Show Context)
Citation Context ...0.00. meshes constitute an effective alternative for distributing global clock signals, and are used in high performance microprocessors [1] such as the Power4 [2], Digital Alpha [3], Intel Pentium 4 =-=[4]-=-, and Xeon [5]. Nevertheless, non-tree clock distribution networks suffer certain drawbacks. These networks are composed of a large number of mesh nodes and unbalanced loads, making these networks dif... |

4 | Meshworks: an efficient framework for planning, synthesis and optimization of clock mesh networks
- Rajaram, Pan
- 2008
(Show Context)
Citation Context ...ocess of adding crosslinks to the clock tree to enhance tolerance and lower power [8],[9]. Yet other papers propose removing some edges from a mesh to reduce power while minimally increasing the skew =-=[10]-=-,[11]. While most of these papers focus on skew variations, the approach proposed in this paper manages skew tolerance based on the criticality of the timing margins. The clocks driving a critical log... |

3 | Restle et al., “The Clock Distribution of the - J - 2002 |

3 |
et al., “Clock Distribution Architectures: a Comparative Study
- Yeh
- 2006
(Show Context)
Citation Context ...ck distribution networks suffer certain drawbacks. These networks are composed of a large number of mesh nodes and unbalanced loads, making these networks difficult to analyze, optimize, and automate =-=[6]-=-,[12],[13]. Routing redundancies require significant resources as compared to optimized tree-based clock distribution networks where point-topoint routing is used [7]. Meshes dissipate higher power [1... |

3 |
Power Dissipation in Basic Global Clock Distribution Networks
- Sobczyk, Luczyk, et al.
- 2007
(Show Context)
Citation Context ...istribution networks suffer certain drawbacks. These networks are composed of a large number of mesh nodes and unbalanced loads, making these networks difficult to analyze, optimize, and automate [6],=-=[12]-=-,[13]. Routing redundancies require significant resources as compared to optimized tree-based clock distribution networks where point-topoint routing is used [7]. Meshes dissipate higher power [12] du... |

2 |
et al., “Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB
- Tam
- 2006
(Show Context)
Citation Context ...onstitute an effective alternative for distributing global clock signals, and are used in high performance microprocessors [1] such as the Power4 [2], Digital Alpha [3], Intel Pentium 4 [4], and Xeon =-=[5]-=-. Nevertheless, non-tree clock distribution networks suffer certain drawbacks. These networks are composed of a large number of mesh nodes and unbalanced loads, making these networks difficult to anal... |

2 | Power Efficient TreeBased Crosslinks for Skew Reduction
- Vaisband, Ginosar, et al.
- 2009
(Show Context)
Citation Context ... non-tree distribution networks have been presented, employing either customized meshes [1–7] or automating the process of adding crosslinks to the clock tree to enhance tolerance and lower power [8],=-=[9]-=-. Yet other papers propose removing some edges from a mesh to reduce power while minimally increasing the skew [10],[11]. While most of these papers focus on skew variations, the approach proposed in ... |

2 |
Clock Skew Evaluation Considering Manufacturing Variability
- Abe, Hashimoto, et al.
- 2008
(Show Context)
Citation Context ...ing is impractical in most mesh structures. Due to delay differences in the drivers, short-circuit current loops are generated across the redundant mesh paths [12]. Increasing process variations [14],=-=[15]-=- dissipate more power, since a more tolerant mesh structure dissipates higher power due to greater use of metal and driver oversizing [15]. Several proposals for optimizing non-tree distribution netwo... |

2 |
A Probabilistic Model for Clock Skew
- Kugelmass, Steiglitz
- 1988
(Show Context)
Citation Context ... uncertainty: As technology scales, the effect of process variations on clock skew is aggravated [14],[15]. Clock skew can be modeled as composed of both deterministic and probabilistic elements [13],=-=[18]-=-. In this work, the following notation is employed. For two sequentially-adjacent registers i and j, the deterministic or nominal skew components is skew i,j nom, and the maximum skew variation of the... |

1 |
Different Approaches for Clock Skew Analysis
- Tosik, Gallego, et al.
- 2007
(Show Context)
Citation Context ...bution networks suffer certain drawbacks. These networks are composed of a large number of mesh nodes and unbalanced loads, making these networks difficult to analyze, optimize, and automate [6],[12],=-=[13]-=-. Routing redundancies require significant resources as compared to optimized tree-based clock distribution networks where point-topoint routing is used [7]. Meshes dissipate higher power [12] due to ... |

1 |
Timing Optimization Through
- Kourtev, Taskin, et al.
- 2009
(Show Context)
Citation Context ...may require that, for instance, the maximum skew will be limited by skew i,j max=µ i,j skew+3·σ i,j skew. Constraint graph: Synchronous circuits are represented as a directed multi-graph G C [1],[16],=-=[17]-=-. Each clock sink is represented by a vertex v i∈GC V, so that GC V = S. Each local data path located between two sequentially-adjacent clock sinks i and j is represented by a weighted edge e i,j∈GC E... |