## COMPARISON OF SIGMA–DELTA CONVERTER CIRCUIT ARCHITECTURES IN DIGITAL CMOS TECHNOLOGY (2004)

### BibTeX

@MISC{Dolev04comparisonof,

author = {Noam Dolev and Avner Kornfeld},

title = {COMPARISON OF SIGMA–DELTA CONVERTER CIRCUIT ARCHITECTURES IN DIGITAL CMOS TECHNOLOGY},

year = {2004}

}

### OpenURL

### Abstract

Integration of analog-to-digital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which have been presented in the literature, consisting of discrete-time and continuous-time integration in voltage-mode and in current-mode. For high resolution, superiority of switched-capacitor circuits over the alternatives is shown, based on process technology considerations. Design guidelines are outlined for selecting oversampling rate and other key parameters, in order to obtain maximal data resolution. Keywords: Analog–digital conversion; sigma–delta modulation; signal-to-noise analysis; low voltage CMOS; switched capacitors; switched current. 1.

### Citations

318 | Analog integrated circuit design,” in - Johns, Martin - 1997 |

62 | The design of sigma-delta modulation analog-to-digital converters - Boser, Wooley - 1988 |

26 |
A use of limit cycle oscillations to obtain robust analog-to-digital converters
- Candy
- 1974
(Show Context)
Citation Context ...order and M is the oversampling ratio. (2) Thermal noise originating from switches at the sampling capacitor CS and the input stage33 is given by: V 2 [ 1 kT th−SC = 2+ M CS 4 ( 1+ 3 α )] ≈ gm 4 kT , =-=(4)-=- M CS where k is the Boltzman constant, T is the absolute temperature, gm is the amplifier transconductance, CS is the sampling capacitor and α is a factor that depends on the amplifier configuration.... |

21 | 1.8V Digital-Audio Sigma-Delta Modulator in 0.8um CMOS
- Rabii
- 1997
(Show Context)
Citation Context ... due to inaccurate sampling time caused by random variations in the clock waveform. 20 Assuming an uncorrelated random process with maximum jitter ∆tmax, weobtain V 2 jt−SC 2 Vpp (2πf0∆tmax) = 12 2 . =-=(6)-=- M Dependence on whether M is the same as for thermal noise: each doubling of the oversampling ratio reduces the jitter noise by 3 dB. In this analysis, we neglect clock feed-through noise, which exis... |

19 | On the stability of sigma-delta modulators - Hein, Zakhor - 1993 |

17 | An Overview of Sigma-Delta Converters - Aziz, Sorensen, et al. - 1996 |

12 | A comparison of modulator networks for high-order oversampling sigma-delta analog-to-digital conversion - Ribner - 1991 |

12 | Top-Down Design of HighPerformance Sigma-Delta Modulators - Medeiro - 1999 |

9 | Second-order sigma-delta modulation for digital-audio signal acquisition - Brandt - 1991 |

7 |
et al., “A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects
- Tyagi
(Show Context)
Citation Context ...igma–delta modulator The operation of this circuit (Fig. 1) is described in Ref. 20. The noise sources are as follows: (1) Quantization noise18 is given by: V 2 ( )(2L+1) 2 1 1 π q−SC = Vpp M 48 2L , =-=(3)-=- (2L +1) where Vpp is the maximum input voltage signal-swing (peak to peak), L is the integrator order and M is the oversampling ratio. (2) Thermal noise originating from switches at the sampling capa... |

7 |
A 1.95-V, 0.34-mW, 12-b sigma-delta modulator stabilized by local feedback loops
- Au, Leung
- 1997
(Show Context)
Citation Context ...nt error that was developed by Dias 36 and using the white-noise approximation, the error expression is given by: V 2 FOC−SI = 1 1 3M g2 {[3 m−in 2 λ1IPP +2λjIPP +2θ √ ]√ (√ ) IPP 3KIPP 3 − 1 K } 2 , =-=(10)-=- where Cdg1 θ = Cdg1 + Cgs1 + C , where λ1 and λj are the short channel effect factor of the sampling transistor and the bias transistor, respectively. From Eq. (10), we can see that the finite output... |

7 | A two path bandpass sigma delta modulator for digital IF extraction at 20 - Ong, Wooley - 1997 |

6 | A third-order currentmode continuous-time sigma–delta modulator, The
- Aboushady, Dessouky, et al.
- 1999
(Show Context)
Citation Context ...s RC filter and is not folded because of sampling. Accordingly, the total input thermal noise is dependent on the sampling frequency. The total thermal noise is given by37 : V 2 th−CT−V =2kTRt(2f0) , =-=(11)-=- where Rt =2R+ 4 ( 1+ 3 α ) 1 , gm gm R is the resistance of the input resistor, gm is the amplifier transconductance and α is a factor that depends on the amplifier configuration and its typical valu... |

6 | Fractal capacitors - Samavati, Hajimiri, et al. - 1998 |

5 |
1 V power supply, low-power consumption A/D conversion technique with swing-suppression noise shaping
- Matsuya, Yamada
- 1994
(Show Context)
Citation Context ...ble noise power is independent of the selected value of sampling capacitor. Eliminating MCs from Eqs. (13) and (14), and assuming that ln(SNR) is approximately constant, we obtain: √ gm SNR ≤ a2VPP . =-=(15)-=- kTf0 In advanced processes gm increases to achieve high speed while the supply voltage drops in order to reduce power dissipation and to protect transistors from high √ electrical fields. The product... |

4 |
A 1.5-V–100-W modulator with 12-b dynamic range using the switched-opamp technique
- Peluso, Steyaert, et al.
- 1997
(Show Context)
Citation Context ...o bandwidth and slew-rate limitations. Assuming that the settling error is uncorrelated with the input signal and uniformly distributed, the settling noise is 33 : V 2 set−SC = Kint 1 M e−gm/2f0MCs , =-=(5)-=-522 N. Dolev, A. Kornfeld & A. Kolodny where Kint = 1 3 ( ISR gm ) 2 ( 1+ CS Cf ) 2 e 2((VPP(CS/Cf )gm)/(ISR(1+(CS/Cf )))−1) , f0 is the input bandwidth, Cf is the feedback capacitor in the integrato... |

4 | A low-voltage switched-current delta-sigma modulator,” under revision for - Tan, Eriksson |

4 | Switched-Current Design and Implementation of Oversampling AID Converters - Tan - 1997 |

4 | Optimal parameters for delta-sigma modulator topologies - Marques, Peluso, et al. - 1998 |

4 | On charge injection in analog MOS switches and dummy switch compensation techniques - Eichenberger, Guggenbuhl - 1990 |

4 | Analytic step response of MOS current mirrors - Nairn - 1993 |

4 | Noise in mixed continuous-time switched-capacitor sigma–delta modulators - Dias, Palmisano, et al. - 1992 |

3 | The effect of integrator leak in sigma–delta modulation - Feely, Chua - 1991 |

2 |
Low-voltage double-sampled sigma delta converters
- Senderowicz, Nicollini, et al.
- 1997
(Show Context)
Citation Context ...s required in this case. 4. Discussion By comparing Figs. 6 and 7, it is evident that second-order discrete-time sigma– delta modulators are limited by quantization noise at low sampling frequencies, =-=(12)-=-528 N. Dolev, A. Kornfeld & A. Kolodny Region 1 - quantization noise is dominant Region 2 - jitter noise is dominant 0 -20 -40 Thermal Quantization Jitter Total noise -60 Noise power -80 -100 -120 -1... |

2 | Temes, Oversampling methods for data conversion - Candy, C - 1991 |

1 |
Trends of the CMOS process technology for system on a chip
- Nishimura
(Show Context)
Citation Context ...beyond the signal band, such that it can be filtered out in the digital domain. If the quantization error were the only problem, the signal-to-noise ratio in any of the circuits would be given by Eq. =-=(1)-=- with the number of quantizer bits n = 1, assuming a sinusoidal input signal and using the well-known white-noise approximation for the quantization error 25 : SNR [dB] =6.02n +1.76 + 10 log [ (M π ) ... |

1 |
Temes, The realization of delta–sigma A/D converters in low-voltage digital
- Grilo, Huang, et al.
- 1998
(Show Context)
Citation Context ...e is given by Eq. (3), with Vpp = Ipp/gm−in, whereIpp is the maximum input current signal swing (peak to peak). (2) Thermal noise is given by 23 : V 2 th−SI = g2 m0 g 2 m−in ( 1 kT 2 1+ M C 3 gmj ) , =-=(7)-=- gm0 where gm0 represents the transconductance of transistors M1, M2 andgmj represents the transconductance of the bias transistor M4. The dependence of thermal noise on the oversampling ratio is simi... |

1 |
A 1.8 V 15-bit 1 mW 2nd-order sigma–delta modulator
- Wei, Salama
(Show Context)
Citation Context ...ion, it is possible to derive the following error expression for settling noise in SI circuit: where V 2 set−SI = 3 g 2 m−in M [ Xmax 5IPP 1+X2 ] 2 max Xmax = 1 6 e−√ 5IPP β/2f0MC , β = µ0COX W L . , =-=(8)-=- Assuming IPP =1/2Ibias, whereibias is the bias current and IPP is the maximum peak-to-peak input current. This result has high similarity to the settling expression in SC topology (5). (4) Clock feed... |

1 |
1.5 V low-power third order continuous-time lowpass sigma delta AD converter
- Gerfers, Manoli
(Show Context)
Citation Context ...to derive the feed-through error expression: V 2 { 1 CFT−SI = K where K = 1 2 µ0COX ∆VOS = COX CS W L , 3Mg 2 m−in +∆VOS − Vt [ − 1 2 WpLpVt − 1 2 WnLn [( CSW ] 2 CS } 2 − 3IPP )(√ ) 3IPP +1 + Vt K , =-=(9)-=- ( ) ( ) VCC − Vt + VDD WpLOVL − WnLOVL ] The second component in Eq. (9) is dependent on the gate voltage and is presented using a coefficient CSW/C, where: CSW = 1 2 COX(WpLp + WnLn) . From this ana... |

1 |
A 900-mV low-power delta sigma A/D converter with 77-dB dynamic range
- Peluso, Vancorenland, et al.
- 1998
(Show Context)
Citation Context ...able noise remains constant. This property can be derived with some simplifications as follows: Thermal noise limits the SNR according to Eq. (4), which can be approximated by SNR 2 ≤ V 2 PP MCS kT . =-=(13)-=- The settling-noise limited SNR can be approximated from Eq. (5), assuming linear settling and ignoring slew-rate, by an expression of the form SNR ≤ a1e gm/f0MCs . (14)530 N. Dolev, A. Kornfeld & A.... |

1 |
A 1 V second order sigma–delta modulator, The
- Grech, Micallef, et al.
- 1999
(Show Context)
Citation Context ...ted by SNR 2 ≤ V 2 PP MCS kT . (13) The settling-noise limited SNR can be approximated from Eq. (5), assuming linear settling and ignoring slew-rate, by an expression of the form SNR ≤ a1e gm/f0MCs . =-=(14)-=-530 N. Dolev, A. Kornfeld & A. Kolodny 100 80 60 40 Total power for sampling capacitor of 1.9pF 20 Noise Power 0 -20 -40 Total power for sampling capacitor of 1pF -60 -80 -100 Total power for samplin... |

1 | 1.2-V, 16-bit audio A/d converter with suppressed latch error noise - Matsuya, Terada - 1997 |

1 | Switched-current oversampling converters - Tan - 1995 |

1 | Fundamental limitations of switched-capacitor sigma–delta modulators - Dias, Palmisano, et al. - 1992 |

1 | Harmonic distortion in switched-current circuits - Martins, Dias, et al. - 1997 |