FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs

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FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs (1994)

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by Jason Cong , Yuzheng Ding

Venue:	IEEE TRANS. CAD
Citations:	317 - 41 self

BibTeX

@ARTICLE{Cong94flowmap:an,
    author = {Jason Cong and Yuzheng Ding},
    title = {FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs},
    journal = {IEEE TRANS. CAD},
    year = {1994},
    volume = {13},
    pages = {1--12}
}

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Abstract

The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. In the past a few years, a number of heuristic algorithms have been proposed for technology mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean networks and little is known about how far their solutions are away from the optimal ones. This paper presents a theoretical breakthrough which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time. A key step in our algorithm is to compute a minimum height Kfeasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUTs by maximizing the volume of each cut and by several post-processing operations. Based on these results, we have implemented an LUT-based FPGA mapping package called FlowMap. We have tested FlowMap on a large set of benchmark examples and compared it with other LUT-based FPGA mapping algorithms for delay optimization, including Chortle-d, MIS-pga-delay, and DAG-Map. FlowMap reduces the LUT network depth by up to 7% and reduces the number of LUTs by up to 50% compared to the three previous methods.

Keyphrases

delay optimization fpga design optimal technology mapping algorithm polynomial time lut-based fpga mapping package minimum height kfeasible cut lut network depth key step depth minimization lut-based fpga mapping algorithm several post-processing operation theoretical breakthrough network flow computation optimal one important technology large set general boolean network benchmark example guarantee optimal solution previous method technology mapping lut-based fpga technology mapping problem vlsi asic heuristic algorithm

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