3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration

3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration (2001)

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by Kaustav Banerjee , Shukri J. Souri , Pawan Kapur , Krishna C. Saraswat

Venue:	Proceedings of the IEEE
Citations:	78 - 5 self

BibTeX

@INPROCEEDINGS{Banerjee013-dics:,
    author = {Kaustav Banerjee and Shukri J. Souri and Pawan Kapur and Krishna C. Saraswat},
    title = {3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration},
    booktitle = {Proceedings of the IEEE},
    year = {2001},
    pages = {602--633}
}

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Abstract

This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D

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