NISC Technology and Preliminary Results (2005)
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BibTeX
@MISC{Reshadi05nisctechnology,
author = {Mehrdad Reshadi and Bita Gorjiara and Daniel Gajski},
title = {NISC Technology and Preliminary Results},
year = {2005}
}
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Abstract
A common way of improving an application’s performance is implementing it on a custom hardware. High level synthesis (HLS) and application specific instruction-set processor are two alternatives for automating this process. HLS techniques usually can handle small programs. Also, since the datapath is not available during scheduling, limited datapath and layout optimizations (such as interconnect pipelining) are possible in HLS. On the other hand, to run an application on a custom hardware, ASIP approaches require the extra phases of designing custom instructions and implementing them in both instruction decoder and compiler. In this report, we present theNISC approach where an application is directly compiled on a given datapath. The compiler does not use any instruction abstraction and directly generates the control signal values of datapath components in each clock cycle. The generated architecture is called No-Instruction-Set-Computer (NISC). In this report, we present the core compiler algorithm followed by two sets of experimental results, one focusing on architecture reuse and the other one on designing a custom architecture for a given application. Having a fine-grained control over the datapath, our compiler can generate up to 70 % better performance compared to an instruction-set- based compiler according to our preliminary results. Also, by designing a custom datapath for DCT algorithm, we could achieve 7 times speedup, 1.64 times power reduction, 12.5 times energy savings, and more than 3 times area reduction compared to a soft-core MIPS implementation. i Contents
Keyphrases
preliminary result nisc technology custom hardware high level synthesis architecture reuse control signal value hl technique time energy saving fine-grained control application performance thenisc approach common way dct algorithm time area reduction application specific instruction-set processor clock cycle interconnect pipelining limited datapath instruction decoder generated architecture custom architecture core compiler algorithm soft-core mips implementation time power reduction experimental result instruction abstraction custom datapath small program custom instruction layout optimization extra phase datapath component
