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Connectivity based Dual Vdd Assignment Algorithm for Power Reduction in FPGA
BibTeX
@MISC{Sekhar_connectivitybased,
author = {G. Veera Sekhar and Jatindra Kumar Deka},
title = {Connectivity based Dual Vdd Assignment Algorithm for Power Reduction in FPGA},
year = {}
}
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Abstract
Abstract — In the past few decades with advancement in VLSI technology, FPGA chip density has increased and FPGA devices now provide a large number of smaller feature size transistors and can support higher clock speeds. While this advancement is beneficial for implementing larger and faster designs within a single chip, it also leads to increased power consumption. With the remarkable growth of FPGA based battery-powered systems, such as personal computing devices, wireless equipment and consumer electronics, low power FPGA design is of increased importance. With this huge continuing increase in FPGA size, its complexity and the new technology emergence has made power estimation and optimization as an ultimate design consideration. In this work, we are supplying dual Vdd to the logic blocks, instead of the single Vdd used in traditional FPGAs. The assignment of dual Vdd(low/high) to a logic block is based on the criticality of the path. We have proposed an alternative algorithm to find out the critical path in the FPGA implementation of the circuit. Depending on the priority of a node in a critical path, we assign low Vdd to a node so that the performance of the circuit remains within the specified limit. Due to the application of low Vdd to some of the nodes in the FPGA implementation, the power consumption is reduced.
Keyphrases
power reduction dual vdd assignment algorithm critical path dual vdd logic block fpga implementation power consumption low vdd feature size transistor increased importance low power fpga design wireless equipment new technology emergence large number remarkable growth fpga size fpga device personal computing device ultimate design consideration vlsi technology battery-powered system alternative algorithm power estimation single chip traditional fpgas specified limit consumer electronics single vdd fpga chip density past decade clock speed
