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Design of power-aware FPGA fabrics (2007)
BibTeX
@MISC{Gayasen07designof,
author = {Aman Gayasen and Suresh Srinivasan and N. Vijaykrishnan and Mahmut Kandemir},
title = {Design of power-aware FPGA fabrics},
year = {2007}
}
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Abstract
We present two techniques to reduce the power consumption in FPGAs. The first technique uses two supply voltages: timing-critical paths run on normal Vdd, while the non-critical ones save power by using a lower Vdd. Our programmable dual-Vdd architectures and Vdd assignment algorithms provide an average power saving of 61 % across the MCNC benchmarks. The second technique targets applications where configuration time is crucial. It uses Asymmetric SRAM (ASRAM) (instead of high-Vt SRAM) cells to implement the configuration memory. Our bit-inversion algorithm further reduces leakage by increasing the number of ASRAM cells that are in their preferred state.
Keyphrases
power-aware fpga fabric power consumption asymmetric sram supply voltage non-critical one bit-inversion algorithm reduces leakage programmable dual-vdd architecture preferred state vdd assignment algorithm first technique high-vt sram normal vdd configuration time asram cell average power saving second technique target application configuration memory timing-critical path mcnc benchmark
