## Formal Verification of the VAMP Floating Point Unit (2001)

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Venue: | In CHARME 2001, volume 2144 of LNCS |

Citations: | 13 - 6 self |

### BibTeX

@INPROCEEDINGS{Berg01formalverification,

author = {Christoph Berg and Christian Jacobi},

title = {Formal Verification of the VAMP Floating Point Unit},

booktitle = {In CHARME 2001, volume 2144 of LNCS},

year = {2001},

pages = {325--339},

publisher = {Springer}

}

### Years of Citing Articles

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### Abstract

We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theorem prover PVS.

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Citation Context ... Xilinx FPGA. Project status. As mentioned above, the FPU we have verified is embedded in the VAMP microprocessor, which is currently being verified at our institute. The VAMP is a variant of the DLX =-=[11, 20]-=-, a 32 bit RISC processor based on the MIPS instruction set. The VAMP processor features a Tomasulo scheduler, delayed branch, a cache memory interface, precise interrupts, and the FPU described in th... |

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Citation Context ...n of a complete microprocessor called VAMP. Part of this microprocessor is a fully IEEE compliant floating point unit (FPU). This paper describes the verification of the FPU in the theorem prover PVS =-=[22]-=-. The FPU we have verified is developed in the textbook on computer architecture by Muller and Paul [20]. The designs go down to the level of single gates. Along with the complete designs come paper p... |

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Citation Context ...4 JACOBI AND BERG Figure 8. PVS implementation of circuit LIMIT and correctness lemmas. This is equivalent to 2 12 − 1 − 〈as〉 =−[as] − 1. Replacing [·] with 〈·〉,wehave 2 12 − 〈as〉 =−(〈as〉 − 2 12 · 〈as=-=[11]-=-〉). This is true because as[11] ⇐⇒ [as] < 0. For [as] ≥ 0, we have to prove [as] = 〈as〉 where as[11] = 0, which is trivial.sFORMAL VERIFICATION OF THE VAMP FLOATING POINT UNIT 255 The second part of t... |

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Citation Context ...ivision algorithms. Miner and Leathrum [18] verify a general class of subtractive division algorithms with respect to the IEEE standard. More mechanized proofs of SRT integer division are reported in =-=[3, 14]-=-. Cornea-Hasegan describes the computation of division and square root by NewtonRaphson iteration in the Intel IA-64 architecture [5, 6]. The verification is done using 1 http://www-wjp.cs.uni-sb.de/p... |

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Citation Context ...the computation of division and square root by Newton-Raphson iteration in the Intel FPUs. The verification is done using paperand-pencil proofs supported by Mathematica, acomputer algebra system. In =-=[13]-=-, Chen et al. verify the correctness of sub-circuits of Intel’s Pentium Pro floating point unit. They leave out the composition of these sub-circuits, and the formal reasoning why this composition is ... |

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Citation Context ...e AMD K5 division algorithm [19] with the theorem prover ACL2. Russinoff has verified the K5 square root algorithm as well as the Athlon multiplication, division, square root, and addition algorithms =-=[24, 25, 27]-=-. In all his verification projects, Russinoff proves the correctness of a register transfer level implementation against his formalization of the IEEE standard using ACL2. Russinoff does not handle ex... |

21 |
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Citation Context ...V to verify a floating point adder. Exceptions and denormals are not handled in both verification projects. Verkest et al. verify a binary non-restoring integer division algorithm [28]. Clarke et al. =-=[7]-=- and Ruess et al. [23] verify SRT division algorithms. Miner and Leathrum [18] verify a general class of subtractive division algorithms with respect to the IEEE standard. More mechanized proofs of SR... |

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Citation Context ...More mechanized proofs of SRT integer division are reported in [3, 14]. Cornea-Hasegan describes the computation of division and square root by NewtonRaphson iteration in the Intel IA-64 architecture =-=[5, 6]-=-. The verification is done using 1 http://www-wjp.cs.uni-sb.de/projects/verification/ Mathematica. O'Leary et al. report on the verification of the gate level design of Intel's FPU using a combination... |

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Citation Context ...g point adder. Exceptions and denormals are not handled in both verification projects. Verkest et al. verify a binary non-restoring integer division algorithm [28]. Clarke et al. [7] and Ruess et al. =-=[23]-=- verify SRT division algorithms. Miner and Leathrum [18] verify a general class of subtractive division algorithms with respect to the IEEE standard. More mechanized proofs of SRT integer division are... |

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Citation Context ...e AMD K5 division algorithm [19] with the theorem prover ACL2. Russinoff has verified the K5 square root algorithm as well as the Athlon multiplication, division, square root, and addition algorithms =-=[24, 25, 27]-=-. In all his verification projects, Russinoff proves the correctness of a register transfer level implementation against his formalization of the IEEE standard using ACL2. Russinoff does not handle ex... |

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Citation Context ...4] use word-level SMV to verify a floating point adder. Exceptions and denormals are not handled in both verification projects. Verkest et al. verify a binary non-restoring integer division algorithm =-=[28]-=-. Clarke et al. [7] and Ruess et al. [23] verify SRT division algorithms. Miner and Leathrum [18] verify a general class of subtractive division algorithms with respect to the IEEE standard. More mech... |

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Citation Context ...emented and tested it on a Xilinx FPGA. The FPU worked on the first try. 1.1. The VAMP project The FPU we have verified is embedded in the VAMP microprocessor which has been verified at our institute =-=[9]-=-. The VAMP is a variant of the DLX [26], a 32-bit RISC processor basedsFORMAL VERIFICATION OF THE VAMP FLOATING POINT UNIT 229 on the MIPS instruction set. The VAMP processor features a Tomasulo sched... |

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Citation Context ...o operations could be designed and verified with small effort given the experience and techniques presented above. Conversion between floating point and decimal formats might be slightly more complex =-=[15, 16]-=-. All three operations raise an unimplemented-trap in the VAMP CPU and may be implemented in a trap handler. 4. FPU control So far we have verified combinatorial circuits. In order to implement the FP... |

12 | Verification of IEEE compliant subtractive division algorithms
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Citation Context ...in both verification projects. Verkest et al. verify a binary non-restoring integer division algorithm [28]. Clarke et al. [7] and Ruess et al. [23] verify SRT division algorithms. Miner and Leathrum =-=[18]-=- verify a general class of subtractive division algorithms with respect to the IEEE standard. More mechanized proofs of SRT integer division are reported in [3, 14]. Cornea-Hasegan describes the compu... |

12 | Formal verification of complex out-of-order pipelines by combining model-checking and theorem-proving
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Citation Context ...g a combination of PVS’s model checking and theorem proving capabilities. We omit the control implementation and verification details here, since they are not specific to FPUs. We refer the reader to =-=[31, 32]-=- for details on the construction and verification of the FPU pipelines.s260 JACOBI AND BERG 5. Implementing the FPU on an FPGA In this section we describe the implementation and test of our FPU on a X... |

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Citation Context ...U have different sources. The vast effort in the verification of the theory of IEEE rounding is due to PVS’s limited arithmetic capabilities. This problem might be solved by new arithmetic strategies =-=[20]-=-; however, these were not available when we did the verification. The most time-consuming part in the verification of the FPU datapaths was the verification on the level of single bits. The verificati... |

10 |
Formal Verification of a Fully IEEE Compliant Floating Point Unit
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Citation Context ...s are subject to rounding as specified in Section 2.2. All four rounding modes must be supported. We have formalized comparisons and conversions in PVS but omit the details here. They can be found in =-=[31]-=-.s246 JACOBI AND BERG Figure 4. Top-level view of the floating point units. 3. Verifying the VAMP FPU In this section, we describe the design and verification of the floating point hardware. The hardw... |

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Citation Context ...do not cover the actual implementation of operations or rounding. Aagaard and Seger combine BDD based methods and theorem proving techniques to verify a floating point multiplier [1]. Chen and Bryant =-=[4]-=- use word-level SMV to verify a floating point adder. Exceptions and denormals are not handled in both verification projects. Verkest et al. verify a binary non-restoring integer division algorithm [2... |

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Citation Context ... processor will be implemented on a Xilinx FPGA. Project Status. As mentioned above, the FPU we have verified is embedded in theVAMP microprocessor, which is currently being verified at our institute =-=[12]-=-. The VAMP is a T. Margaria and T. Melham (Eds.): CHARME 2001, LNCS 2144, pp. 325–339, 2001. c○ Springer-Verlag Berlin Heidelberg 2001s326 C. Berg and C. Jacobi variant of the DLX [9,17], a 32 bit RIS... |

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Citation Context .... Then by lemma 3.9, it holds [2 0 f b ] (P+1) = 2 (P+2) = [2 f b ] (P+1) ut Adder hardware. The adder (Fig. 2) is a straightforward implementation of the described algorithm using basic components [2=-=]-=-. If a subtraction is to be performed, s b is negated, yielding s 0 b . Circuit EXPSUB computes the difference as := e a e b and the flag eb gt ea := (e b > e a ). The result's exponent e s is selecte... |

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Citation Context ...fied the designs with respect to a formalization of the IEEE standard 754 [12] (hereafter called "the standard"). We have partly used the formalization of the standard and the theory of roun=-=ding from [8, 20-=-], particularly the notion of factorings, round decomposition, and -equivalence. Other parts of our IEEE formalization are influenced by Miner's formalization of the standard in PVS [17], particularly... |

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Citation Context ...algorithms. Among other circuits, they verify floating point square root, division, and remainder operations. They do not give details on the specification against which the circuits are verified. In =-=[33]-=-, Kaivola and Kohatsu report on the verification of Intel’s Pentium 4 floating point divider. The main focus of their paper is not the actual divider verification, but the challenges formal verificati... |

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Citation Context ...ery efficient computation of representatives (respectively their IEEE-factorings) by or-ing the less significant bits in an OR-tree, and replacing them by the sticky-bit. This technique is well known =-=[-=-9], but introducing the formalism with -representatives allows for a very concise argumentation about these sticky-computations. The valuable property of -representatives is that rounding x and its re... |

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Citation Context ...ivision algorithms. Miner and Leathrum [18] verify a general class of subtractive division algorithms with respect to the IEEE standard. More mechanized proofs of SRT integer division are reported in =-=[3, 14]-=-. Cornea-Hasegan describes the computation of division and square root by NewtonRaphson iteration in the Intel IA-64 architecture [5, 6]. The verification is done using 1 http://www-wjp.cs.uni-sb.de/p... |

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Citation Context ...ace, precise interrupts, and the FPU described in this paper. The verification of an in-order CPU core is complete, the verification of the Tomasulo out-of-order core will be completed in a few weeks =-=[15]-=-. The verification of the cache has just begun. The verification of the combinatorial floating point circuits is complete. We are currently working on the verification of the FPU pipeline control. Our... |

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Citation Context ...roving [21]. Denormals and exceptions are not covered in the paper. Their definition of rounding is not directly related to the IEEE standard. Moore et al. have verified the AMD K5 division algorithm =-=[19]-=- with the theorem prover ACL2. Russinoff has verified the K5 square root algorithm as well as the Athlon multiplication, division, square root, and addition algorithms [24, 25, 27]. In all his verific... |

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Citation Context ...o operations could be designed and verified with small effort given the experience and techniques presented above. Conversion between floating point and decimal formats might be slightly more complex =-=[15, 16]-=-. All three operations raise an unimplemented-trap in the VAMP CPU and may be implemented in a trap handler. 4. FPU control So far we have verified combinatorial circuits. In order to implement the FP... |

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Citation Context ...cal textbook fashion. We have specified and verified the designs on the gate level in PVS. The paper-and-pencil proofs in [41] served as guidelines ∗ This article is a revised and extended version of =-=[6, 30]-=-. † The work reported in this article was done while the author was affiliated with Saarland University. ‡ Supported by the DFG graduate program Leistungsgarantien für Rechnersysteme.s228 JACOBI AND B... |

5 | z/Architecture: Principles of Operation - IBM - 2000 |

5 | Formal verification of the Pentium R○ 4 floatingpoint multiplier
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Citation Context ... of Intel’s Pentium 4 floating point divider. The main focus of their paper is not the actual divider verification, but the challenges formal verification has to overcome in an industrial setting. In =-=[34]-=-, Kaivola and Narasimhan describe the formal verification of the Pentium 4 multiplier from a similar perspective. The verification covers exception signals, but does not cover denormal numbers. Cornea... |

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Citation Context ... is informal in [8, 20], we use a formal definition of rounding, which is based on Miners formalization of the standard [17]. Harrison has formalized the IEEE standard in the theorem prover HOL Light =-=[10-=-]. Both Miner and Harrison have no direct counterpart to the decomposition theorem and -equivalence (cf. Sect. 2). They do not cover the actual implementation of operations or rounding. Aagaard and Se... |

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Citation Context ...More mechanized proofs of SRT integer division are reported in [3, 14]. Cornea-Hasegan describes the computation of division and square root by NewtonRaphson iteration in the Intel IA-64 architecture =-=[5, 6]-=-. The verification is done using 1 http://www-wjp.cs.uni-sb.de/projects/verification/ Mathematica. O'Leary et al. report on the verification of the gate level design of Intel's FPU using a combination... |

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Citation Context ...ormalization of the IEEE standard that we use is based on [8, 17, 20]. The notion of factorings, round decomposition, and -equivalence is taken from [8, 20]. We have formally verified this theory in [=-=13]-=-. Since the definition of the rounding function is informal in [8, 20], we use a formal definition of rounding, which is based on Miners formalization of the standard [17]. Harrison has formalized the... |

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Citation Context ...ion against his formalization of the IEEE standard using ACL2. Russinoff does not handle exceptions and denormals in his publications; however, he states that he handles denormals in unpublished work =-=[26]. The-=- definition of sticky in [19, 27] corresponds to our rounding of representatives. 2 IEEE Floating Point Arithmetic To formally verify the correctness of a FPU, we need a formal notion of "correct... |

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Citation Context ...r tests of our FPU against the Intel FPU we have encountered differences in the rounding of denormal numbers, which are due to discrepancies of Intel’s rounding to the IEEE standard (Section 5.2). In =-=[1]-=-, Aagaard et al. report on the verification of gate-level implementations of iterative algorithms. Among other circuits, they verify floating point square root, division, and remainder operations. The... |

1 | A hierarchical verification of the IEEE-754 table-driven floating-point exponential function using HOL
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Citation Context ...son proves the correctness of an algorithm for the exponential function against his IEEE formalization. He assumes that IEEE-correct addition, multiplication, and rounding to integer are provided. In =-=[3, 4]-=-, Abdel-Hamid et al. verify an implementation of this algorithm against a formal specification. However, this specification is nearer to the gate-level implementation than to a high-level formalizatio... |

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Citation Context ...son proves the correctness of an algorithm for the exponential function against his IEEE formalization. He assumes that IEEE-correct addition, multiplication, and rounding to integer are provided. In =-=[3, 4]-=-, Abdel-Hamid et al. verify an implementation of this algorithm against a formal specification. However, this specification is nearer to the gate-level implementation than to a high-level formalizatio... |

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Citation Context ... language Verilog. The combinatorial hardware is described in PVS as exemplarily shown in figure 8. For the handling of clocked circuits and more details about the translation, we refer the reader to =-=[8]-=-. Using the pvs2hdl tool, we have implemented all three FPUs on a Xilinx Virtex-E2000 FPGA. The complete hardware was automatically generated, except for the interface hardware needed for the communic... |

1 |
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Citation Context ...the actual destination, the double rounding effect described above can occur. Hence, both Intel’s/AMD’s FPU behavior as well as our behavior is IEEE compliant. The described problem is known to Intel =-=[23]-=-. Intel’s Itanium architecture allows the programmer to control both significand precision and exponent width, thus enabling to choose real double or single precision behavior without the extended pre... |