Realization of Multiple-Output Functions by Reconfigurable Cascades (2001)
| Venue: | INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS (ICCD’01 |
| Citations: | 7 - 5 self |
BibTeX
@INPROCEEDINGS{Iguchi01realizationof,
author = {Yukihiro Iguchi and Tsutomu Sasao and Munehiro Matsuura},
title = {Realization of Multiple-Output Functions by Reconfigurable Cascades},
booktitle = {INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS (ICCD’01},
year = {2001},
pages = {388--393},
publisher = {}
}
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Abstract
A realization of multiple-output logic functions using a RAM and a sequencer is presented. First, a multiple-output function is represented by an encoded characteristic function for non-zeros (ECFN). Then, it is represented by a cascade of look-up tables (LUTs). And finally, the cascade is simulated by a RAM and a sequencer. Multiple-output functions for benchmark functions are realized by cascades of LUTs, and the number of LUTs and levels of cascades are shown. A partition method of outputs for parallel evaluation is also presented. A prototype has been developed by using RAM and FPGA. This realization uses time domain multiplexing, and is useful for the case where the number of output pins is limited.
