Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits (1996)
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BibTeX
@MISC{Rogenmoser96stochasticmethods,
author = {Robert Rogenmoser and Hubert Kaeslin and Tobias Blickle},
title = {Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits},
year = {1996}
}
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Abstract
. The performance of a CMOS circuit depends heavily on its transistor sizes. We have tested a standard optimizer, a Monte Carlo scheme and a method based on Genetic Algorithms combined with very accurate SPICE simulations to automatically optimize transistor sizes of three different digital CMOS circuits. While the standard optimizer and the Monte Carlo scheme are advantageous for small circuits, the method based on Genetic Algorithms was found to be more stable for larger circuits. 1 Introduction Transistor size optimization is a traditional obligation in VLSI (Very Large Scale Integration) design. It is used to improve the performance of a circuit to achieve a design goal in a specific technology. This design goal can either be boosting operating speed, lowering power consumption, or lowering area requirements. In this context the netlist of the circuit is already determined, only the width and the length of the MOS (Metal Oxide Semiconductor) transistors can be adjusted. The figure...
