Abstract

Semiconductor manufacturing process variations are worsening with continued reduction in transistor feature sizes. However, technology scaling is the engine driving the semiconductor industry and must continue. When variations worsen to the point that they can no longer be addressed solely at the device and circuit levels, the next logical step is to develop variation-tolerant microarchitectures. This thesis presents research on modeling, characterizing, and mitigating the impact of process variations on the energy-efficiency of modern chip-multiprocessors. New models are developed for how variations impact chip-multiprocessor power and performance at a variety of granularities, from within a single core to among dies in a speed bin. These numerical models, fit to HSPICE data, achieve orders of magnitude lower error than the analytical models traditionally used in microarchitecture-level research. These models are used to drive the motivation and evaluation of two new schemes for reclaiming some of the energy-efficiency that is lost to process variations, both predicated on addressing variation in static power. Variation-aware level selection (VALS) works in the context of dynamic voltage/frequency scaling (DVFS), a popular method for improving energy-efficiency. In fine-grained

Citations