## An analog VLSI chip for estimating the focus of expansion (1996)

Venue: | In 1997 ISSCC Digest of Technical Papers |

Citations: | 6 - 1 self |

### BibTeX

@TECHREPORT{Mcquirk96ananalog,

author = {Ignacio Sean Mcquirk},

title = {An analog VLSI chip for estimating the focus of expansion},

institution = {In 1997 ISSCC Digest of Technical Papers},

year = {1996}

}

### Years of Citing Articles

### OpenURL

### Abstract

### Citations

303 |
Analysis and Design of Analog Integrated Circuits, 4 th Edition
- Gray, Hurst, et al.
- 2001
(Show Context)
Citation Context ... mos transistor relating the gate to source voltage V gs to the drain current I d : I d =sC ox W 2L (V gs \Gamma V t ) 2 (3:52) we can derive the DC transfer characteristic of the source coupled pair =-=[50]-=-: \DeltaI out =sC ox W 2L (\DeltaV in ) s ` 2Is(C ox W=2L) ' \Gamma (\DeltaV in ) 2 (3:53) This expression is only valid when both transistors are in saturation. To satisfy this requirement, we must h... |

197 |
Principles of CMOS VLSI design: a systems perspective
- Weste, Eshraghian
- 1985
(Show Context)
Citation Context ...f the masking shift register used to shift in the mask bits is shown in Figure 3-32. It is a simple modification of a standard static latch based structure, employing 2-phase non-overlapping clocking =-=[51]-=-. It is composed of two identical sub-blocks, each one driven by one of the phases, and each of these sub-blocks consists of an inverter pair with some pass gates. When the appropriate clock phase is ... |

172 |
The Art of Electronics
- Horowitz, Hill
- 1989
(Show Context)
Citation Context ... ref provides a constant current input to the mirror, helping to keep its bandwidth up at low signal levels. The output of the mirror is also held at a virtual null due to the output I-to-V converter =-=[72]-=-. Thus, each leg of the differential input current is injected into a virtual null, eliminating differential errors due to output conductance. The load capacitance at the inverting node of the output ... |

79 |
Optimum Design
- Arora
- 1989
(Show Context)
Citation Context ...m (E x ; E y ), we note that (\Deltax; \Deltay; ffi 1 ; ffi 2 ; ffi 3 ; ffi 4 ) is confined to a 6D unit hypercube, and we would like to find max(\Deltap) over this hypercube. From linear programming =-=[67]-=-, we know that if a solution exists, it lies at the vertices of the hypercube. Hence, we can evaluate \Deltap at the vertices to find the maximum. Examining the allowed (E x ; E y ) due to the vertice... |

71 |
Temes, Analog MOS Integrated Circuits for Signal Processing
- Gregorian, C
- 1986
(Show Context)
Citation Context ...amplifier designed to buffer the position encoder output as shown in Figure 3-44, both for driving off-chip as well as the on-chip multipliers. It is based on a fairly standard mos two-stage topology =-=[69]-=-, where compensation is done using a source follower and a feedback capacitor. 10pF was used as a conservative estimate of the capacitance the operational amplifier will have to drive. Figures 3-46 an... |

57 |
A precise four-quadrant multiplier with subnanosecond response
- Gilbert
- 1968
(Show Context)
Citation Context ...differential current. The four-quadrant bipolar multiplier based on the translinear principle and shown in Figure 3-36 has dominated the industry since its invention by Barrie Gilbert in the late 60s =-=[55, 56]-=-. The core of this topology is formed from six matched bipolar transistors. The four bipolars on the right have a DC transfer characteristic of [50] \DeltaI out = \DeltaI 2 tanh ` \DeltaV 2V th ' (3:7... |

28 |
A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation
- Bult, Wallinga
- 1987
(Show Context)
Citation Context ...rformance of translinear circuits, so this is a viable option. However, the size of the available bipolar is substantial, and an mos current-mode circuit is preferable. Such a circuit is described in =-=[54]-=- and is the topology we use on the foe chip. The basic three transistor core is shown in Figure 3-34. Clearly, the bias voltage V b set up by the bias current I 0 in the two transistor bias tree is V ... |

22 | Internal cam era calibration using rotation and geom etric shapes
- Stein
- 1993
(Show Context)
Citation Context ... when the foe is near the image boundary, and its parameters should be estimated as well. 5.2.3 Camera Calibration using Rotation The method we use for estimating the camera parameters is detailed in =-=[78]-=- and involves performing calibration from image data only; no actual measurements of object distances or sizes in the real world need be done. If we rotate a camera about an axis\Omega =(\Omega x ;\Om... |

17 |
A high-performance monolithic multiplier using active feedback
- Gilbert
- 1974
(Show Context)
Citation Context ...s: \DeltaI out = \DeltaI 1 \DeltaI 2 I (3:74) To have voltage input, one can generate the differential currents using transconductors. This bipolar structure is still very much the topology of choice =-=[57, 53, 58, 59, 47]-=-, so much so that in many classic analog circuit texts it is required reading [50, 60]. Unfortunately, we cannot 3.5. Circuit Structures 83 + - DV in D out D out I/2 + I /2 I/2 - I /2 in D I/2 + I /2 ... |

16 |
A new wide-band amplifier technique
- Gilbert
- 1968
(Show Context)
Citation Context ...differential current. The four-quadrant bipolar multiplier based on the translinear principle and shown in Figure 3-36 has dominated the industry since its invention by Barrie Gilbert in the late 60s =-=[55, 56]-=-. The core of this topology is formed from six matched bipolar transistors. The four bipolars on the right have a DC transfer characteristic of [50] \DeltaI out = \DeltaI 2 tanh ` \DeltaV 2V th ' (3:7... |

15 |
Bipolar and MOS Analog Integrated Circuit Design
- Grebene
- 1984
(Show Context)
Citation Context ...tial currents using transconductors. This bipolar structure is still very much the topology of choice [57, 53, 58, 59, 47], so much so that in many classic analog circuit texts it is required reading =-=[50, 60]-=-. Unfortunately, we cannot 3.5. Circuit Structures 83 + - DV in D out D out I/2 + I /2 I/2 - I /2 in D I/2 + I /2 in D I/2 - I /2 Figure 3-37: A simple MOS version of the Gilbert multiplier. use bipol... |

15 |
Operational Amplifiers: Theory and Practice
- Roberge
- 1975
(Show Context)
Citation Context ...network around the op-amp to roll off inside the bandwidth of the op-amp, causing stability problems. Hence, compensation with a gain peaking capacitor is required in practice to stabilize the op-amp =-=[73]-=-. The output s abs from the absolute value channel is a single-ended current flowing into nchannel devices on the foe chip and hence the AD7886 for this channel is configured for the unipolar 0-10V ra... |

12 |
A monolithic 16-channel analog array normalizer
- Gilbert
- 1984
(Show Context)
Citation Context ...s: \DeltaI out = \DeltaI 1 \DeltaI 2 I (3:74) To have voltage input, one can generate the differential currents using transconductors. This bipolar structure is still very much the topology of choice =-=[57, 53, 58, 59, 47]-=-, so much so that in many classic analog circuit texts it is required reading [50, 60]. Unfortunately, we cannot 3.5. Circuit Structures 83 + - DV in D out D out I/2 + I /2 I/2 - I /2 in D I/2 + I /2 ... |

10 |
A MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers
- Song, Kim
- 1990
(Show Context)
Citation Context ...n designing multipliers in mos. These topologies fall into two basic categories: approaches based on the Gilbert multiplier [61, 62, 63] and approaches based on the so called quarter-square technique =-=[64, 52, 65, 66]-=-. In the approaches based on the Gilbert topology, the pre-distortion circuit is omitted entirely, and the remaining core of four bipolars is replaced with mos devices. The resulting circuit has a sig... |

10 |
Grounding and Shielding Techniques in Instrumentation
- Morrison
- 1967
(Show Context)
Citation Context ...h, and sensitive measurements were delayed until the transient effects had dissipated. Analog and digital grounds were also tied together in the standard star configuration at the system power supply =-=[75, 76]-=-. 4.3.4 Later Enhancements In the course of testing the foe chip, the FCP was constantly reconfigured to serve a variety of purposes. The flexibility of the system often was sufficient to accomplish w... |

9 |
A Versatile CMOS Linear Transconductor/Square-Law Function Circuit
- Seevinck, Wassenaar
- 1987
(Show Context)
Citation Context ...we need a circuit whose characteristic provides a square. Since the mos transistor is a square-law device, achieving an output current which is the square of an input voltage is a natural application =-=[52]-=-. Furthermore, one common approach to linearization of the source coupled pair that we have discussed is to add a quadratic term into the tail current [49]. However, we need a circuit which operates w... |

8 |
Nonlinear Circuits Handbook," Analog Devices
- Sheingold
- 1974
(Show Context)
Citation Context ...discussed is to add a quadratic term into the tail current [49]. However, we need a circuit which operates with current input. Certainly, we can use translinear circuits to accomplish such a function =-=[47, 53]-=-. These types of circuits are based on the logarithmic nature of the bipolar transistor, and indeed the Orbit process includes vertical npns, albeit without the usual collector implant to reduce colle... |

8 |
A MOS Four-Quadrant Analog Multiplier Using the Quarter-Square Technique
- Pena-Finol, Connelly
- 1987
(Show Context)
Citation Context ...n designing multipliers in mos. These topologies fall into two basic categories: approaches based on the Gilbert multiplier [61, 62, 63] and approaches based on the so called quarter-square technique =-=[64, 52, 65, 66]-=-. In the approaches based on the Gilbert topology, the pre-distortion circuit is omitted entirely, and the remaining core of four bipolars is replaced with mos devices. The resulting circuit has a sig... |

7 |
AFour-Quadrant NMOS Analog Multiplier
- Soo, Meyer
- 1982
(Show Context)
Citation Context ...e, so we need an mos version. Much effort has been invested over the years in designing multipliers in mos. These topologies fall into two basic categories: approaches based on the Gilbert multiplier =-=[61, 62, 63]-=- and approaches based on the so called quarter-square technique [64, 52, 65, 66]. In the approaches based on the Gilbert topology, the pre-distortion circuit is omitted entirely, and the remaining cor... |

7 |
A 20-V four-Quadrant CMOS Analog Multiplier
- Babanezhad, Temes
- 1985
(Show Context)
Citation Context ...e, so we need an mos version. Much effort has been invested over the years in designing multipliers in mos. These topologies fall into two basic categories: approaches based on the Gilbert multiplier =-=[61, 62, 63]-=- and approaches based on the so called quarter-square technique [64, 52, 65, 66]. In the approaches based on the Gilbert topology, the pre-distortion circuit is omitted entirely, and the remaining cor... |

5 |
An *5-V CMOS analog multiplier
- Qin, Geiger
- 1987
(Show Context)
Citation Context ...e, so we need an mos version. Much effort has been invested over the years in designing multipliers in mos. These topologies fall into two basic categories: approaches based on the Gilbert multiplier =-=[61, 62, 63]-=- and approaches based on the so called quarter-square technique [64, 52, 65, 66]. In the approaches based on the Gilbert topology, the pre-distortion circuit is omitted entirely, and the remaining cor... |

5 | A CMOS Four-Quadrant Analog Multiplier
- Bult, Wallinga
- 1986
(Show Context)
Citation Context ...n designing multipliers in mos. These topologies fall into two basic categories: approaches based on the Gilbert multiplier [61, 62, 63] and approaches based on the so called quarter-square technique =-=[64, 52, 65, 66]-=-. In the approaches based on the Gilbert topology, the pre-distortion circuit is omitted entirely, and the remaining core of four bipolars is replaced with mos devices. The resulting circuit has a sig... |

3 |
and T.R.Viswanathan, â€•Design of Linear Transconductance Elements
- Nedungadi
- 1984
(Show Context)
Citation Context ...s of their outputs necessary to implement Equation 3.51. There are many possible circuits to implement the necessary voltage to current transduction, many of which offer excellent range and linearity =-=[47, 48, 49]-=-. Unfortunately, the size constraints imposed by the level of integration we are attempting are formidable, and make the simplicity of the design paramount. Furthermore, the least-squares nature of th... |

3 |
et al. User Guide for Minpack-1
- More
- 1980
(Show Context)
Citation Context ...nciple distance f , the location of the optic axis (c x ; c y ) as well as the distortion parameters (K 1 ; K 2 ) and the two rotation axes using the LMDIF routine from the MINPACK-1 software package =-=[79]-=-. From the two rotation axes estimated by the program, we can additionally estimate the rotation OE in the distal mount. Typical calibration results are shown in Table 5-3. The results of the calibrat... |

1 |
Translinear Circuits
- Gilbert
- 1981
(Show Context)
Citation Context ...s: \DeltaI out = \DeltaI 1 \DeltaI 2 I (3:74) To have voltage input, one can generate the differential currents using transconductors. This bipolar structure is still very much the topology of choice =-=[57, 53, 58, 59, 47]-=-, so much so that in many classic analog circuit texts it is required reading [50, 60]. Unfortunately, we cannot 3.5. Circuit Structures 83 + - DV in D out D out I/2 + I /2 I/2 - I /2 in D I/2 + I /2 ... |

1 |
Device Electronis for Integrated Circuits
- Muller, Kamins
- 1986
(Show Context)
Citation Context ... gate drive of 6V , this would require a device size of W=L = 1=12. However, at the large gate drive we are using, the transistors exhibit a factor of 2 mobility reduction due to mobility degradation =-=[68]-=-. This increases the resistiveness of the devices, so only half the length is required. Hence, the triode transistors were sized at W=L = 1=6 = 6m=36m to provide the appropriate resistance. The two di... |

1 |
A System Demonstration of VLSI Early Vision Processors
- Eshghi
- 1992
(Show Context)
Citation Context ...yncs Parallel Interface Motor Controller Output Bit Motor Controller Input Bit Figure 4-8: Block diagram and floorplan of the foe system board. 4.3. The Electrical Subsystem 107 MIT Vision Chip Group =-=[71]-=-. The A/D and D/A pods in this system were expected to do the level shifting and scaling necessary for interfacing to test boards built around the high speed analog machine vision chips designed by ou... |

1 |
A new wide-band ampli er technique
- Gilbert
- 1968
(Show Context)
Citation Context ... di erential current. The four-quadrant bipolar multiplier based on the translinear principle and shown in Figure 3-36 has dominated the industry since its invention by Barrie Gilbert in the late 60s =-=[55, 56]-=-. The core of this topology is formed from six matched bipolar transistors. The four bipolars on the right havea DC transfer characteristic of [50] Iout = I2 tanh V 2Vth (3:72) where V is the voltage ... |

1 |
Operational Ampli ers: Theory and Practice
- Roberge
- 1975
(Show Context)
Citation Context ...k network around the op-amp to roll o inside the bandwidth of the op-amp, causing stability problems. Hence, compensation with a gain peaking capacitor is required in practice to stabilize the op-amp =-=[73]-=-. The output sabs from the absolute value channel is a single-ended current owing into nchannel devices on the foe chip and hence the AD7886 for this channel is con gured for the unipolar 0-10V range.... |