Performance benefits of monolithically stacked 3-D FPGA (2007)
Cached
Download Links
- [www-isl.stanford.edu]
- [www.stanford.edu]
- DBLP
Other Repositories/Bibliography
| Venue: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Citations: | 14 - 6 self |
BibTeX
@ARTICLE{Lin07performancebenefits,
author = {Mingjie Lin and Student Member and Abbas El Gamal and Yi-chang Lu and Simon Wong},
title = {Performance benefits of monolithically stacked 3-D FPGA},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
year = {2007},
pages = {216--229}
}
Bookmark
 |
 |
 |
 |
 |
 |
OpenURL
Abstract
Abstract—The performance benefits of a monolithically stacked three-dimensional (3-D) field-programmable gate array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing logic blocks (LBs) and interconnects, are investigated. A Virtex-II-style two-dimensional (2-D) FPGA fabric is used as a baseline architecture to quantify the relative improvements in logic density, delay, and power consumption achieved by such a 3-D FPGA. It is assumed that only the switch transistor and configuration memory cells can be moved to the top layers and that the 3-D FPGA employs the same LB and programmable interconnect architecture as the baseline 2-D FPGA. Assuming they are ≤ 0.7, the area of a static random-access memory cell and switch transistors having the same characteristics as n-channel metal–oxide–semiconductor devices in the CMOS layer are used. It is shown that a monolithically stacked 3-D FPGA can achieve 3.2 times higher logic density, 1.7 times lower critical path delay, and 1.7 times lower total dynamic power consumption than the baseline 2-D FPGA fabricated in the same 65-nm technology node. Index Terms—Field-programmable gate arrays (FPGAs), monolithically stacked, performance, three-dimensional (3-D). I.
