## Formal Reasoning with Verilog HDL (1998)

Venue: | In Workshop on Formal Techniques for Hardware and Hardware-like Systems, Marstrand |

Citations: | 8 - 2 self |

### BibTeX

@INPROCEEDINGS{Pace98formalreasoning,

author = {Gordon J. Pace and Jifeng He},

title = {Formal Reasoning with Verilog HDL},

booktitle = {In Workshop on Formal Techniques for Hardware and Hardware-like Systems, Marstrand},

year = {1998}

}

### OpenURL

### Abstract

Most hardware verification techniques tend to fall under one of two broad, yet separate caps: simulation or formal verification. This paper briefly presents a framework in which formal verification plays a crucial role within the standard approach currently used by the hardware industry. As a basis for this, the formal semantics of Verilog HDL are defined, and properties about synchronization and mutual exclusion algorithms are proved.

### Citations

63 |
A calculus of durations
- Zhou, Hoare, et al.
- 1991
(Show Context)
Citation Context ...lly oriented. Figure 2 contrasts a behavioural with a structural description of a negation gate. 3.2 Approach Taken The semantics of Verilog are described using a variant of Discrete Duration Calculus=-=[14,12, 8]-=-. Rather than using the normal chop operator we define an alternative sequential composition operator which takes into consideration nonstable states. The resulting Relational Duration Calculus is sim... |

36 |
Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines
- Börger, Glässer, et al.
- 1995
(Show Context)
Citation Context ...ulation and verification: a unified approach 2 VHDL and Verilog Until now, most work done in the formalization of industry standard hardware simulation languages has almost exclusively dealt with VHDL=-=[1, 2, 4, 5, 9, 11]-=-. The main problem is that all of this research refers back to the original informal semantics description in the official documentation, leading to possible discrepancies. In comparison, until quite ... |

34 | The Semantic Challenges of Verilog HDL
- Gordon
- 1995
(Show Context)
Citation Context ...r results than would otherwise be expected. Hopefully, this will also reduce the diversity of methods used by different research groups and thus increase the rate at which information is built up. In =-=[6]-=-, M.J.C. Gordon presented a semi-informal description of the semantics of Verilog preceding most major work on the language. This may help to provide a common stepping-stone out of the informal docume... |

27 |
Chopping a point
- Chaochen, Hansen
- 1996
(Show Context)
Citation Context ... than using the normal chop operator we define an alternative sequential composition operator which takes into consideration nonstable states. The resulting Relational Duration Calculus is similar to =-=[13]-=- and [10]. Duration Calculus. Only a brief overview of Duration Calculus (DC) will be given here. Readers interested in fuller accounts of the calculus may refer to [7]. Boolean States and Expressions... |

13 |
A formalization of the VHDL simulation cycle
- Tassel
- 1992
(Show Context)
Citation Context ...ulation and verification: a unified approach 2 VHDL and Verilog Until now, most work done in the formalization of industry standard hardware simulation languages has almost exclusively dealt with VHDL=-=[1, 2, 4, 5, 9, 11]-=-. The main problem is that all of this research refers back to the original informal semantics description in the official documentation, leading to possible discrepancies. In comparison, until quite ... |

12 | editors. Semantics of VHDL
- Kloos, Breuer
- 1995
(Show Context)
Citation Context ...ulation and verification: a unified approach 2 VHDL and Verilog Until now, most work done in the formalization of industry standard hardware simulation languages has almost exclusively dealt with VHDL=-=[1, 2, 4, 5, 9, 11]-=-. The main problem is that all of this research refers back to the original informal semantics description in the official documentation, leading to possible discrepancies. In comparison, until quite ... |

10 |
Z description of duration calculus
- Brien, Engel, et al.
- 1993
(Show Context)
Citation Context ...uration Calculus is similar to [13] and [10]. Duration Calculus. Only a brief overview of Duration Calculus (DC) will be given here. Readers interested in fuller accounts of the calculus may refer to =-=[7]-=-. Boolean States and Expressions: DC is a temporal logic allowing one to state properties pertaining to time in a straightforward and natural fashion. The basic building blocks of the calculus are sta... |

8 |
A denotational definition of the VHDL simulation Kernel
- Davis
- 1993
(Show Context)
Citation Context |

8 |
VHDL verification in the State Delta Verification System (SDVS
- Filippenko
- 1991
(Show Context)
Citation Context |

6 | Semantics and verification of extended phase transition systems in duration calculus
- Qiwen
- 1997
(Show Context)
Citation Context ...ng the normal chop operator we define an alternative sequential composition operator which takes into consideration nonstable states. The resulting Relational Duration Calculus is similar to [13] and =-=[10]-=-. Duration Calculus. Only a brief overview of Duration Calculus (DC) will be given here. Readers interested in fuller accounts of the calculus may refer to [7]. Boolean States and Expressions: DC is a... |

5 |
Chaochen: Duration Calculi: An Overview
- Zhou
- 1993
(Show Context)
Citation Context ...lly oriented. Figure 2 contrasts a behavioural with a structural description of a negation gate. 3.2 Approach Taken The semantics of Verilog are described using a variant of Discrete Duration Calculus=-=[14,12, 8]-=-. Rather than using the normal chop operator we define an alternative sequential composition operator which takes into consideration nonstable states. The resulting Relational Duration Calculus is sim... |

3 |
Simulating hardware specifications within a theorem proving environment
- Camilleri
- 1990
(Show Context)
Citation Context ...ation. Combining the two together can provide a very powerful working environment, which provides both the flexibility and concept grasping of simulators and the rigorous background of formal methods =-=[3]-=-. Simulation allows faster development of design and cheaper and easier debugging during the design stage than if formal verification is used. The proliferation of standard hardware description langua... |

2 |
Formal Semantics for VHDL. Number 307
- Kloos, Breuer
- 1995
(Show Context)
Citation Context |