Formal Reasoning with Verilog HDL (1998)
by
Gordon J. Pace
,
Jifeng He
| Venue: | In Workshop on Formal Techniques for Hardware and Hardware-like Systems, Marstrand |
| Citations: | 8 - 2 self |
BibTeX
@INPROCEEDINGS{Pace98formalreasoning,
author = {Gordon J. Pace and Jifeng He},
title = {Formal Reasoning with Verilog HDL},
booktitle = {In Workshop on Formal Techniques for Hardware and Hardware-like Systems, Marstrand},
year = {1998}
}
Bookmark
 |
 |
 |
 |
 |
 |
OpenURL
Abstract
Most hardware verification techniques tend to fall under one of two broad, yet separate caps: simulation or formal verification. This paper briefly presents a framework in which formal verification plays a crucial role within the standard approach currently used by the hardware industry. As a basis for this, the formal semantics of Verilog HDL are defined, and properties about synchronization and mutual exclusion algorithms are proved.
Citations
| 58 | A.P.: A calculus of durations - Zhou, Hoare, et al. - 1991 |
| 34 | Formal definition of an abstract VHDL’93 simulator by EAmachines - Glässer, Börger, et al. - 1995 |
| 32 | The Semantic Challenge of Verilog HDL - Gordon - 1995 |
| 27 | Chopping a point - Chaochen, Hansen - 1996 |
| 13 | A Formalization of the VHDL Simulation Cycle - Tassel - 1993 |
| 12 | editors. Semantics of VHDL - Kloos, Breuer - 1995 |
| 10 | Z description of duration calculus - Brien, Engel, et al. - 1993 |
| 8 | A denotational definition of the VHDL simulation Kernel - Davis - 1993 |
| 8 | VHDL verification in the State Delta Verification System (SDVS - Filippenko - 1991 |
| 6 | Semantics and verification of extended phase transition systems in duration calculus - Qiwen - 1997 |
| 5 | Chaochen: Duration Calculi: An Overview - Zhou - 1993 |
| 3 | Simulating hardware specifications within a theorem proving environment - Camilleri - 1990 |
| 2 | Formal Semantics for VHDL. Number 307 - Kloos, Breuer - 1995 |
