An Efficient Technique for Exploring Register File Size in ASIP Design

An Efficient Technique for Exploring Register File Size in ASIP Design (2004)

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by Manoj Kumar Jain , M. Balakrishnan , Anshul Kumar

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@MISC{Jain04anefficient,
    author = {Manoj Kumar Jain and M. Balakrishnan and Anshul Kumar},
    title = {An Efficient Technique for Exploring Register File Size in ASIP Design},
    year = {2004}
}

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Abstract

Performance estimation is a crucial operation which drives the design space exploration in Application Specific Instruction Set Processor (ASIP) synthesis. With the increase in the level of integration, the design space has considerably expanded which makes the simulation driven techniques inadequate due to their slow speed. Alternatively, there are approaches which estimate performance by scheduling the application on the available processor resources without generating code. These are much more effective in exploring a large design space.

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