## Algorithmic Aspects of Symbolic Switch Network Analysis (1987)

Venue: | IEEE Trans. CAD/IC |

Citations: | 19 - 5 self |

### BibTeX

@ARTICLE{Bryant87algorithmicaspects,

author = {Randal E. Bryant},

title = {Algorithmic Aspects of Symbolic Switch Network Analysis},

journal = {IEEE Trans. CAD/IC},

year = {1987},

volume = {6},

pages = {618--633}

}

### OpenURL

### Abstract

A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean equations. For the class of networks that arise when analyzing digital metal-oxide semiconductor (MOS) circuits, a simple pivot selection rule guarantees that most s switch networks encountered in practice can be solved with O(s) operations. When represented by a directed acyclic graph, the set of Boolean formulas generated by the analysis has total size bounded by the number of operations required by the Gaussian elimination. This paper presents the mathematical basis for systems of Boolean equations, their solution by Gaussian elimination, and data structures and algorithms for representing and manipulating Boolean formulas.

### Citations

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Citation Context ...owever, several approaches yield practical results in many instances. One approach uses a different representation of Boolean functions that makes equivalence testing more straightforward. The author =-=[36]-=- has devised a representation based on a different type of directed acyclic graph that is canonical, i.e., a given function has a unique representation. Equivalence testing then becomes a simple matte... |

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Citation Context ... in terms of systems of equations defined over a Boolean algebra. It parallels previous work on the symbolic analysis of contact networks [8], and more general algebraic formulations of path problems =-=[13, 14, 15, 16]-=-. The presentation differs from previous ones in several respects. First, Boolean algebra is selected as the domain of interest. This gives properties that more general presentations cannot assume, in... |

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Citation Context ...o evaluate to 1, while y evaluates to 0. The redundancy test attempts to prove this property by contradiction, in a manner reminiscent of an automatic theorem prover based on the Resolution Principle =-=[33]-=-. That is, it assigns value 1 to x, 0 to y, and determines the logical consequences of these assignments. If it reaches a contradiction, then the formulas are ordered, otherwise they are assumed unord... |

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Citation Context ...tween n \Gamma 1 and 2n \Gamma 1 edges. Hence, this result shows that an the analysis of an s switch network requires O(s) operations when the network has a GSP structure. A survey of 4 books on VLSI =-=[25, 26, 27, 28]-=-, plus a direct analysis of many circuit designs has uncovered only a handful of non-GSP channel graphs, as illustrated in Figures 6, 7, 8 and 9. Figure 6 shows the graph for a section of the carry ch... |

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Citation Context ...ny GSP graph can be generated by starting with a single vertex and applying a sequence of these rules. Much has been written on strategies for choosing elimination orderings, including both empirical =-=[21, 22] and theor-=-etical [23] results. In general, the problem of selecting an optimalsordering is NP-complete [18]. However, we would be satisfied with a "good", but not necessarily optimal, ordering, and we... |

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Citation Context ...ated by starting with a single vertex and applying a sequence of these rules. Much has been written on strategies for choosing elimination orderings, including both empirical [21, 22] and theoretical =-=[23]-=- results. In general, the problem of selecting an optimal ordering is NP-complete [18]. However, we would be satis ed with a \good", but not necessarily optimal, ordering, and we can exploit propertie... |

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Citation Context ...s. The leaves denote variables and constants, while the nodes denote Boolean operations. A formula is denoted by a pointer to a node. 6.1 DAG Representation of Formulas A directed acyclic graph (DAG) =-=[31, 32]-=- resembles a parse tree, with leaves representing either variables or constants, and with internal nodes representing Boolean operations. In a DAG, however, a given subgraph may be shared by several b... |

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A Symbolic Analysis of Relay and Switching Circuits
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Citation Context ...rcuits were constructed with electromechanical relays. Shannon, in the first application of Boolean algebra to digital systems, developed several techniques for analyzing a switch network symbolically=-=[1]-=-. For a network of switches, each of which is either open or closed depending on the value of some Boolean variable, the goal of symbolic analysis is to derive formulas expressing the conditions under... |

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Citation Context ...ian Elimination Gaussian elimination provides the most efficient known method for solving sparse Boolean systems, where Boolean operations replace the real arithmetic used when solving linear systems =-=[13, 20]-=-. Figure 1 shows a sketch of the Gaussian elimination algorithm. The code has two parts: forward elimination and back substitution. Forward elimination successively modifies the system structure, each... |

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Citation Context ...of Figure 17 illustrates, greedy pivot selection tends to yield "long, skinny" formulas without much potential for concurrent evaluation. On the other hand, pivot selection based on nested d=-=issection [23, 35] yields &q-=-uot;short, fat" formulas, many terms of which could be evaluated simultaneously. In particular, the family of GSP graphs satisfies a 2-separator theorem, meaning that it is always possible to fin... |

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Citation Context ...tween n \Gamma 1 and 2n \Gamma 1 edges. Hence, this result shows that an the analysis of an s switch network requires O(s) operations when the network has a GSP structure. A survey of 4 books on VLSI =-=[25, 26, 27, 28]-=-, plus a direct analysis of many circuit designs has uncovered only a handful of non-GSP channel graphs, as illustrated in Figures 6, 7, 8 and 9. Figure 6 shows the graph for a section of the carry ch... |

72 |
A Unified Approach to Path Problems
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Citation Context ... in terms of systems of equations defined over a Boolean algebra. It parallels previous work on the symbolic analysis of contact networks [8], and more general algebraic formulations of path problems =-=[13, 14, 15, 16]-=-. The presentation differs from previous ones in several respects. First, Boolean algebra is selected as the domain of interest. This gives properties that more general presentations cannot assume, in... |

70 |
Topology of series-parallel networks
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Citation Context ... separately. Most channel graphs describing digital MOS circuits fall into a restricted class that we shall term "general series-parallel" (GSP). This class extends conventional series-paral=-=lel graphs[24]-=- to include those containing acyclic branches. GSP graphs can be defined inductively starting with a single vertex as the basis, and applying the production rules illustrated 12 @ @ \Gamma \Gamma A A ... |

59 |
A switch-level model and simulator for MOS digital systems
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Citation Context ... is formed from the supply or ground to the gate output[2, 3, 4]. More complex MOS models take into account such effects as resistance ratios, dynamic memory, and invalid or uninitialized logic values=-=[5, 6]-=-. A companion paper [7] shows that even with these more elaborate models, the behavior of a MOS circuit can be determined by analyzing a series of switch networks. Thus the symbolic analysis of switch... |

36 |
An algebra for network routing problems
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Citation Context ... in terms of systems of equations defined over a Boolean algebra. It parallels previous work on the symbolic analysis of contact networks [8], and more general algebraic formulations of path problems =-=[13, 14, 15, 16]-=-. The presentation differs from previous ones in several respects. First, Boolean algebra is selected as the domain of interest. This gives properties that more general presentations cannot assume, in... |

24 |
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(Show Context)
Citation Context |

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(Show Context)
Citation Context ...of the art in symbolic analysis has not kept up with these demands. For example, most published symbolic analysis methods for MOS circuits start by enumerating all possible simple paths in the network=-=[9, 10, 11]-=-. A second method involves enumerating the possible sets of connected components formed in the switch network for different values of the control variables [12]. This approach can also produce a descr... |

14 |
Digital CMOS Circuit Design
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(Show Context)
Citation Context ...tween n \Gamma 1 and 2n \Gamma 1 edges. Hence, this result shows that an the analysis of an s switch network requires O(s) operations when the network has a GSP structure. A survey of 4 books on VLSI =-=[25, 26, 27, 28]-=-, plus a direct analysis of many circuit designs has uncovered only a handful of non-GSP channel graphs, as illustrated in Figures 6, 7, 8 and 9. Figure 6 shows the graph for a section of the carry ch... |

12 |
A unified switching theory with applications to VLSI design
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- 1982
(Show Context)
Citation Context ... is formed from the supply or ground to the gate output[2, 3, 4]. More complex MOS models take into account such effects as resistance ratios, dynamic memory, and invalid or uninitialized logic values=-=[5, 6]-=-. A companion paper [7] shows that even with these more elaborate models, the behavior of a MOS circuit can be determined by analyzing a series of switch networks. Thus the symbolic analysis of switch... |

12 |
Introduction to Switching and Automata Theory, McGraw-Hill
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(Show Context)
Citation Context ... a set A is denoted W a2A a. The sum of an empty set is defined to equal 0. Symbolic Switch Network Analysis 5 Elements of B are partially ordered as bsa when b a = a, i.e., by their lattice ordering =-=[2, 17]-=-. This partial ordering obeys the following properties, as can easily be derived from the laws of Boolean algebra: Proposition 1 For any b 2 A bsa2A a Proposition 2 If bsa for all a 2 A then bsa2A a: ... |

12 |
personal communication
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(Show Context)
Citation Context ...it designs has uncovered only a handful of non-GSP channel graphs, as illustrated in Figures 6, 7, 8 and 9. Figure 6 shows the graph for a section of the carry chain circuit from the MIPS-X processor =-=[29]-=-. Even when repeated for a number of stages, systems with this graph have linear elimination complexity, because no vertex has elimination degree greater than 3. The same holds for pass transistor par... |

11 |
Processor e cient parallel solution of linear systems over an abstract eld
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(Show Context)
Citation Context ...of Figure 17 illustrates, greedy pivot selection tends to yield \long, skinny" formulas without much potential for concurrent evaluation. On the other hand, pivot selection based on nested dissection =-=[23, 35]-=- yields \short, fat" formulas, many terms of which could be evaluated simultaneously. In particular, the family of GSP graphs satis es a 2-separator theorem, meaning that it is always possible to nd 2... |

10 |
Simulation of MOS circuits by decision diagrams
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(Show Context)
Citation Context ...ssible simple paths in the network[9, 10, 11]. A second method involves enumerating the possible sets of connected components formed in the switch network for di erent values of the control variables =-=[12]-=-. This approach can also produce a description of size exponential in the number of transistors. These accounts indicate little progress since Shannon's day. In general, a MOS circuit can be partition... |

7 |
Logic equations for MOSFET circuits
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(Show Context)
Citation Context ...of the art in symbolic analysis has not kept up with these demands. For example, most published symbolic analysis methods for MOS circuits start by enumerating all possible simple paths in the network=-=[9, 10, 11]-=-. A second method involves enumerating the possible sets of connected components formed in the switch network for different values of the control variables [12]. This approach can also produce a descr... |

6 |
Symbolic Logic Simulation
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(Show Context)
Citation Context ...of the art in symbolic analysis has not kept up with these demands. For example, most published symbolic analysis methods for MOS circuits start by enumerating all possible simple paths in the network=-=[9, 10, 11]-=-. A second method involves enumerating the possible sets of connected components formed in the switch network for different values of the control variables [12]. This approach can also produce a descr... |

4 | Sparsity-Directed Decomposition for Gaussian Elimination on Matrices
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- 1970
(Show Context)
Citation Context ...ny GSP graph can be generated by starting with a single vertex and applying a sequence of these rules. Much has been written on strategies for choosing elimination orderings, including both empirical =-=[21, 22] and theor-=-etical [23] results. In general, the problem of selecting an optimalsordering is NP-complete [18]. However, we would be satisfied with a "good", but not necessarily optimal, ordering, and we... |

3 |
Simulation of MOS Circuits by Decision Diagrams
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- 1985
(Show Context)
Citation Context ...sible simple paths in the network[9, 10, 11]. A second method involves enumerating the possible sets of connected components formed in the switch network for different values of the control variables =-=[12]-=-. This approach can also produce a description of size exponential in the number of transistors. These accounts indicate little progress since Shannon's day. In general, a MOS circuit can be partition... |

2 |
Boolean Matrices and Combinational Circuit Design
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- 1955
(Show Context)
Citation Context ...of significant size. Furthermore, there was no concern about data structures and algorithms for representing and manipulating Boolean formulas. Even more recent methods based on matrix representations=-=[8]-=- do not address these algorithmic issues. Today symbolic analysis methods are to be executed by computers on networks containing thousands of switches. To implement an analyzer, every detail of repres... |

2 |
Tarjan, "Generalized Nested Dissection
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- 1979
(Show Context)
Citation Context ...ated by starting with a single vertex and applying a sequence of these rules. Much has been written on strategies for choosing elimination orderings, including both empirical [21, 22] and theoretical =-=[23] results. -=-In general, the problem of selecting an optimalsordering is NP-complete [18]. However, we would be satisfied with a "good", but not necessarily optimal, ordering, and we can exploit properti... |

2 |
A Uni ed Approach toPath Problems
- Tarjan
- 1981
(Show Context)
Citation Context ...m in terms of systems of equations de ned over a Boolean algebra. It parallels previous work on the symbolic analysis of contact networks [8], and more general algebraic formulations of path problems =-=[13, 14, 15, 16]-=-. The presentation di ers from previous ones in several respects. First, Boolean algebra is selected as the domain of interest. This gives properties that more general presentations cannot assume, inc... |

1 |
Implication Algorithms for Switch Level
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- 1982
(Show Context)
Citation Context ...ogic gates in MOS treat transistors as simple switches and define the behavior of a gate in terms of the conditions under which a conducting path is formed from the supply or ground to the gate output=-=[2, 3, 4]-=-. More complex MOS models take into account such effects as resistance ratios, dynamic memory, and invalid or uninitialized logic values[5, 6]. A companion paper [7] shows that even with these more el... |

1 |
Boolean Analysis of MOS Circuits, companion paper
- Bryant
- 1987
(Show Context)
Citation Context ... or ground to the gate output[2, 3, 4]. More complex MOS models take into account such effects as resistance ratios, dynamic memory, and invalid or uninitialized logic values[5, 6]. A companion paper =-=[7]-=- shows that even with these more elaborate models, the behavior of a MOS circuit can be determined by analyzing a series of switch networks. Thus the symbolic analysis of switch networks remains as a ... |

1 |
Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine
- Spillinger, Silberman
- 1986
(Show Context)
Citation Context ...The first method requires solving the NP-hard problem of testing Boolean formulas for equivalence [18], while the second requires \Theta(jV j \Delta jEj) steps, except for restricted graph structures =-=[19]-=-. 5.1 Gaussian Elimination Gaussian elimination provides the most efficient known method for solving sparse Boolean systems, where Boolean operations replace the real arithmetic used when solving line... |

1 |
A Uni ed Switching Theory with Applications to VLSI Design
- Hayes
- 1982
(Show Context)
Citation Context ...h is formed from the supply or ground to the gate output[2, 3, 4]. More complex MOS models take into account such e ects as resistance ratios, dynamic memory, and invalid or uninitialized logic values=-=[5, 6]-=-. A companion paper [7] shows that even with these more elaborate models, the behavior of a MOS circuit can be determined by analyzing a series of switch networks. Thus the symbolic analysis of switch... |

1 |
Du n, \Topology of Series-Parallel Networks
- J
- 1965
(Show Context)
Citation Context ... separately. Most channel graphs describing digital MOS circuits fall into a restricted class that we shall term \general series-parallel" (GSP). This class extends conventional series-parallel graphs=-=[24]-=- to include those containing acyclic branches. GSP graphs can be de ned inductively starting with a single vertex as the basis, and applying the production rules illustrated ws12 A A A ; @ @ ;A A AAA ... |

1 |
The TheoryofParsing,Translation
- Aho, Ullman
- 1972
(Show Context)
Citation Context ...as. The leaves denote variables and constants, while the nodes denote Boolean operations. A formula is denoted by apointer to a node. 6.1 DAG Representation of Formulas A directed acyclic graph (DAG) =-=[31, 32]-=- resembles a parse tree, with leaves representing either variables or constants, and with internal nodes representing Boolean operations. In aDAG, however, a given subgraph may be shared by several br... |