Abstract

To ensure that hardware descriptions are synthesizable, designers today bear the responsibility of understanding and conforming to coding guidelines. This makes it harder to write reusable designs, and makes the transition from a behavioral design to a structural design more labor intensive. This paper proposes the use of a static analysis to check the synthesizability of a design. This static analysis uses ideas from statically-typed two-level languages to reflect the distinction between values that are known at design time and values that are carried on wires in synthesized circuits. This distinction is crucial for determining whether abstractions such as iteration and module parameters are used in a synthesizable manner. To formalize these ideas, we develop a core calculus for Verilog, along with a static type system. We define a preprocessing step that defines how such abstractions can be eliminated in an early phase of synthesis, and the kinds of errors that can occur during preprocessing. Our key technical result is showing that a well-typed design cannot lead to preprocessing errors, and can only expand to a synthesizable circuit. 1

Citations