## Sequential Synthesis Using S1S (2000)

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Venue: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |

Citations: | 15 - 7 self |

### BibTeX

@INPROCEEDINGS{Aziz00sequentialsynthesis,

author = {Adnan Aziz and Felice Balarin and Robert K. Brayton and Alberto Sangiovanni-Vincentelli},

title = {Sequential Synthesis Using S1S},

booktitle = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

year = {2000}

}

### Years of Citing Articles

### OpenURL

### Abstract

We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to problems arising in the synthesis and optimization of synchronous digital hardware. Specifically, we derive a logical expression which yields a single finite state automaton characterizing the set of implementations that can replace a component of a larger design. The power of our approach is demonstrated by the fact that it generalizes immediately to arbitrary interconnection topologies, and to designs containing nondeterminism and fairness. We also describe control aspects of sequential synthesis and relate controller realizability to classical work on program synthesis and tree automata.

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Citation Context ... 0, , . • Well formed formulas: , where and are terms, and and are well-formed formulas. Examples: , , , , . A variable occurs freely in a formula, if it appears in the formula, and is not quantifie=-=d [9]-=-. We write to indicate that at most occur freely in . In the sequel, we will refer to well formed formulas simply as formulas. We will routinely use the symbols , etc., as logical abbreviations, and d... |

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Citation Context ...[33]–[35]. Similar problems have been considered in the control community under the label “model matching” [6], in the discrete event system (DES) community under the label “supervisory contro=-=l” [37] [25], and -=-in concurrency theory they appear ass1150 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 10, OCTOBER 2000 “scheduler synthesis” [36] and “equation so... |

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Citation Context ...mization of the entire system. This is for designs specified at the structural level in the form of netlists, or at the behavioral level, i.e., in the form of finite state machines (FSMs). De Micheli =-=[21]-=- gives an excellent introduction to logic synthesis. Designs invariably consist of a set of interacting components. The environment of a particular component gives rise to a certain amount of flexibil... |

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Citation Context ...s that can replace a particular component which is part of a larger design. The power of our approach is seen by the fact that it can be applied to designs containing nondeterminism and fairness [8], =-=[18]-=-, and also to arbitrary interconnection topologies. Optimization of compositional designs may result in combinational cycles, i.e., loops consisting solely of gates. Even though such loops can sometim... |

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Citation Context ...tural numbers with the successor function; the term “second order” refers to the fact that the logic refers to both subsets as well as individual natural numbers. It was studied in detail by Büch=-=i in [2]; -=-in particular it was shown to be decidable. S1S provides an extremely powerful mechanism for analyzing and manipulating sequential systems—the expressiveness of logic (conjunction, negation, and qua... |

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Citation Context ...g a logical specification, and checking if there exists a model which satisfies it. The model depends on the context; for example, it could be a Turing machine program [20], a finite state transducer =-=[23]-=-, or a dataflow graph [1]. The issues involved in this discipline include decidability, complexity, and expressiveness of the specification language. In this paper we will be mostly concerned with the... |

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Citation Context ... and checking if there exists a model which satisfies it. The model depends on the context; for example, it could be a Turing machine program [20], a finite state transducer [23], or a dataflow graph =-=[1]-=-. The issues involved in this discipline include decidability, complexity, and expressiveness of the specification language. In this paper we will be mostly concerned with the optimization problem; we... |

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Citation Context ...ps can sometimes be used to optimize circuits, it is considered good design practice to avoid them, because cyclic circuits are difficult to analyze, and can have undesired oscillatory behaviors [3], =-=[19], [2-=-9]. Guided by design practice, we identify flexibility available for synthesis while ensuring that cycles of logic will not be introduced by optimization. The term “synthesis” is used in the theor... |

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Citation Context ...ogically characterize the flexibility that can be used to optimize components in hierarchical designs. The relationship to the more classical view of program synthesis in the form of Church’s proble=-=m [24]-=-, automata on trees, and fairness is described in Section V. We summarize our contributions in Section VI and suggest a number of ways of extending our results. II. FORMAL MODELS FOR HARDWARE In order... |

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Citation Context ...nce %(cf. the remarks in Section I). Testing language containment for nondeterministic finite state automata is PSPACE complete; we could have used a stronger notion for conformance, e.g., simulation =-=[32]-=- which can be tested in polynomial time. If we did so, the development of the E-machine would be quite different. Such an approach could reduce complexity, at the cost of completeness. D. Optimization... |

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Citation Context ...ng this, complementation is relatively straightforward. The determinization step, while similar in spirit to the subset construction for -automata [13], is extremely complex. The best known procedure =-=[27] st-=-arts with a nondeterministic Büchi automaton on states, and yields a Büchi automaton with states in the worst case. For an -language over accepted by a Büchi automaton, projected down to is also ac... |

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Citation Context ...ng FSM is minimum state. Not surprisingly, this is closely related to the problem of minimizing an incompletely specified finite state machine (ICFSM)sAZIZ et al.: SEQUENTIAL SYNTHESIS USING S1S 1159 =-=[12]-=-. However, there is a subtle distinction: for an incompletely specified FSM, at a given state, for a specific input, either the next-state and output is fixed, or any output and next-state is allowed.... |

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Citation Context ...ity criteria (e.g., minimum state [15]). For combinational designs, the problem of determining and using the flexibility afforded by “don’t care” conditions is well solved both in theory and pra=-=ctice [28]-=-. We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to probl... |

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Citation Context ...in [35]. Compared to supervisory control of DES [25], our approach offers the advantage of being compatible with FSM techniques that have seen continuous developments in the past three decades (e.g., =-=[16]-=- and [35]), provides more natural model of reactive system, and allows significantly simpler development of results. We have chosen input-output language containment as a correctness criterion because... |

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Citation Context ...ad hoc, incomplete, and, sometimes, simply incorrect. The constructions and proofs offered are often extremely cumbersome. This is witnessed by a number of previous papers [10], [26], [5], [17], [33]�=-=��[35]. Simila-=-r problems have been considered in the control community under the label “model matching” [6], in the discrete event system (DES) community under the label “supervisory control” [37] [25], and... |

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Citation Context ...nded to be ad hoc, incomplete, and, sometimes, simply incorrect. The constructions and proofs offered are often extremely cumbersome. This is witnessed by a number of previous papers [10], [26], [5], =-=[17], [33]–[-=-35]. Similar problems have been considered in the control community under the label “model matching” [6], in the discrete event system (DES) community under the label “supervisory control” [37... |

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Citation Context ...igns has tended to be ad hoc, incomplete, and, sometimes, simply incorrect. The constructions and proofs offered are often extremely cumbersome. This is witnessed by a number of previous papers [10], =-=[26], [5], [-=-17], [33]–[35]. Similar problems have been considered in the control community under the label “model matching” [6], in the discrete event system (DES) community under the label “supervisory c... |

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Citation Context ...as tended to be ad hoc, incomplete, and, sometimes, simply incorrect. The constructions and proofs offered are often extremely cumbersome. This is witnessed by a number of previous papers [10], [26], =-=[5], [17], -=-[33]–[35]. Similar problems have been considered in the control community under the label “model matching” [6], in the discrete event system (DES) community under the label “supervisory contro... |

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Citation Context ...h loops can sometimes be used to optimize circuits, it is considered good design practice to avoid them, because cyclic circuits are difficult to analyze, and can have undesired oscillatory behaviors =-=[3], [1-=-9], [29]. Guided by design practice, we identify flexibility available for synthesis while ensuring that cycles of logic will not be introduced by optimization. The term “synthesis” is used in the... |

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Citation Context ...ign had an output differing from that in the original design, there is a surrounding environment which could observe the change and as a result function incorrectly. Following the parlance of Singhal =-=[30], we-=- will refer to implementations satisfying this condition as being “safe replacements” for the component. However, this characterization is not well suited for synthesis; we want a finite structure... |

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Citation Context ...of all possible implementations is characterized using some finite structure (which is the topic of this paper); consequently, one is chosen according to some optimality criteria (e.g., minimum state =-=[15]). For-=- combinational designs, the problem of determining and using the flexibility afforded by “don’t care” conditions is well solved both in theory and practice [28]. We propose the use of the logic ... |

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Citation Context ...to describe the process of taking a logical specification, and checking if there exists a model which satisfies it. The model depends on the context; for example, it could be a Turing machine program =-=[20]-=-, a finite state transducer [23], or a dataflow graph [1]. The issues involved in this discipline include decidability, complexity, and expressiveness of the specification language. In this paper we w... |

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Citation Context ...n to that for -automata can be applied. The complement of a language accepted by a Büchi automaton is also accepted by a Büchi automaton, although the proof of this fact is nontrivial. An early proo=-=f [4] proc-=-eeds by taking the (possibly nondeterministic) defining Büchi automaton and creating a deterministic finite state automaton with a “Muller” acceptance condition [31], which accepts the same langu... |

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Citation Context ...e. Here, we differ from most of the previous approaches in the process algebra settings, where a much stronger relation, typically some form of bisimulation equivalence is used [22]. The exception is =-=[14]-=- which offers a general framework where the satisfaction relation is not set a priori, but can be defined by a formula in a logic that can express, among other relations, both simulation and bisimulat... |

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Citation Context ...17], [33]–[35]. Similar problems have been considered in the control community under the label “model matching” [6], in the discrete event system (DES) community under the label “supervisory c=-=ontrol” [37] [25],-=- and in concurrency theory they appear ass1150 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 10, OCTOBER 2000 “scheduler synthesis” [36] and “equati... |

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Citation Context ...al designs has tended to be ad hoc, incomplete, and, sometimes, simply incorrect. The constructions and proofs offered are often extremely cumbersome. This is witnessed by a number of previous papers =-=[10], [26], -=-[5], [17], [33]–[35]. Similar problems have been considered in the control community under the label “model matching” [6], in the discrete event system (DES) community under the label “supervi... |

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Citation Context ...n concurrency theory they appear ass1150 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 10, OCTOBER 2000 “scheduler synthesis” [36] and “equation sol=-=ving” [22]-=-. Compared to model matching approaches [6] we limit somewhat the choice of possible controllers. The limitation is not serious in hardware context, because it rules out only those circuits that resul... |

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Citation Context ... sometimes be used to optimize circuits, it is considered good design practice to avoid them, because cyclic circuits are difficult to analyze, and can have undesired oscillatory behaviors [3], [19], =-=[29]. Gu-=-ided by design practice, we identify flexibility available for synthesis while ensuring that cycles of logic will not be introduced by optimization. The term “synthesis” is used in the theoretical... |

2 |
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(Show Context)
Citation Context ...o be ad hoc, incomplete, and, sometimes, simply incorrect. The constructions and proofs offered are often extremely cumbersome. This is witnessed by a number of previous papers [10], [26], [5], [17], =-=[33]–[35]. S-=-imilar problems have been considered in the control community under the label “model matching” [6], in the discrete event system (DES) community under the label “supervisory control” [37] [25]... |

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