## Analytical Delay Models for VLSI Interconnects Under Ramp Input (1996)

### Cached

### Download Links

- [vlsicad.ucsd.edu]
- [ftp.cs.ucla.edu]
- [ftp.cs.ucla.edu]
- [www.cs.york.ac.uk]
- [www.cecs.uci.edu]
- [nexus6.cs.ucla.edu]
- DBLP

### Other Repositories/Bibliography

Venue: | IEEE ICCAD |

Citations: | 20 - 7 self |

### BibTeX

@INPROCEEDINGS{Kahng96analyticaldelay,

author = {Andrew B. Kahng and Kei Masuko and Sudhakar Muddu},

title = {Analytical Delay Models for VLSI Interconnects Under Ramp Input},

booktitle = {IEEE ICCAD},

year = {1996},

pages = {30--36}

}

### Years of Citing Articles

### OpenURL

### Abstract

Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical RLC interconnectionswith ramp input, Elmore delay can deviate by up to 100 % or more from SPICEcomputed delay since it is independent of rise time of the input ramp signal. We develop new analytical delay models based on the first and second moments of the interconnect transfer function when the input is a ramp signal with finite rise time. Delay estimates using our first moment based analytical models are within 4 % of SPICE-computed delay, and models based on both first and second moments are within 2:3 % of SPICE, across a wide range of interconnect parameter values. Evaluation of our analytical models is several orders of magnitude faster than simulation using SPICE. We also describe extensions of our approach for estimation of source-sink delays in arbitrary interconnect trees.

### Citations

385 |
Asymptotic Waveform Evaluation for Timing Analysis
- Pillage, Rohrer
- 1990
(Show Context)
Citation Context ...bitrary interconnect structures, but impedance (Figure 1) can be obtained using ABCD parameters [1] as are computationally expensive. Faster methodsbased on moment matching techniques are proposed in =-=[12, 13, 14, 17]-=-, but are still too expen1 sive to be used during layout optimization. Thus, Elmore delay [2], a H(s) = h ZS first order approximation of delay understep input, is still the most widely cosh(θh)+ Z0 u... |

366 |
The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers
- Elmore
- 1948
(Show Context)
Citation Context ... computationally expensive. Faster methodsbased on moment matching techniques are proposed in [12, 13, 14, 17], but are still too expen1 sive to be used during layout optimization. Thus, Elmore delay =-=[2]-=-, a H(s) = h ZS first order approximation of delay understep input, is still the most widely cosh(θh)+ Z0 used delay model in the performance-driven synthesis of clock distribution and Steiner global ... |

180 | Signal delay in RC tree networks
- Rubinstein, eld, et al.
- 1983
(Show Context)
Citation Context ...S and load impedance ZT . By considering only one pole in the transfer function, i.e, approximating the denominator polynomial to only the first moment, the single pole response can be obtained as in =-=[4, 15]-=-. The single pole of the transfer function is equal to the inverse of the Elmore delay TED. Hence, the delay at arbitrary thresholds of the single pole response can be directly related to Elmore delay... |

84 | Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI - Sakurai - 1993 |

71 | Approximation of Wiring Delay in MOSFET LSI - Sakurai - 1983 |

50 | Timing models for MOS circuits - Horowitz - 1984 |

38 | High-performance routing trees with identified critical sinks - Boese, Kahng, et al. - 1993 |

33 | Transient simulation of lossy interconnects based on the recursive convolution formulation - Lin, Kuh - 1992 |

25 |
Modern Transmission Line Theory and Application
- Dworsky
- 1979
(Show Context)
Citation Context ...ransfer function of an RLC interconnect line with source and load give the most accurate insight into arbitrary interconnect structures, but impedance (Figure 1) can be obtained using ABCD parameters =-=[1]-=- as are computationally expensive. Faster methodsbased on moment matching techniques are proposed in [12, 13, 14, 17], but are still too expen1 sive to be used during layout optimization. Thus, Elmore... |

25 | Efficient Transient Simulation of Lossy Interconnect - Roychowdhury, Pederson |

18 | AWESpice: A General Tool for the Accurate and Efficient Simulation of Interconnect - Raghavan, Bracken, et al. - 1992 |

16 | A simplified synthesis of transmission lines with a tree structure
- Zhou, Su, et al.
- 1994
(Show Context)
Citation Context ...5: Variation of factor F2 = b1 ,1 b (1 , e 1 =T b1 R ) with respect to TR TR . 5 Two-PoleAnalysis The two-pole methodology for interconnect response computation under step input has been discussed in =-=[4, 7, 20]-=-. For interconnect trees (or lines) the transfer function has a special form in which the numerator polynomial is a constant, i.e., approximating to s2 term yields H(s) 1 1+sb1+s2b2 . For the case of ... |

14 |
Exact moment matching model of transmission lines and application to interconnect delay estimation
- Yu, Kuh
- 1995
(Show Context)
Citation Context ...function moment computation for the main path. The k th 6 Our model is not limited to traditional segment models, and accuracy of our results would likely improve if we use non-uniform segment models =-=[7, 19]-=- designed to perfectly match the low-order moments of the distributed RLC line.S R S V N+1 R N L N Y N V N Figure 6: Representation of the main path in the tree, where each distributed line is modele... |

12 | Pillage, "RICE: Rapid Interconnect Circuit Evaluator - Ratzlaff, Gopal, et al. - 1991 |

12 | Fast Approximation of the Transient Response of Lossy Transmission Line Trees - Sriram, Kang - 1993 |

11 |
Analytical Delay Models for VLSI
- Kahng, Masuko, et al.
- 1996
(Show Context)
Citation Context ...and capacitance per unit length and h is the length of the line. The variables bk are called the coefficients of the transfer function and are directly related to the moments of the transfer function =-=[8]-=-. Expanding the transfer function into a Maclaurin series of s around s = 0 leads to an infinite series, and to compute the response the series is truncated to desired order. The method of Padé approx... |

7 | Signal propagation delay in RC models for interconnect - Wyatt - 1987 |

6 |
Waveform moment methods for improved interconnection analysis
- McCormick, Allen
- 1990
(Show Context)
Citation Context ...s to an infinite series, and to compute the response the series is truncated to desired order. The method of Padé approximation has been widely used to compute the response from the transfer function =-=[11, 12]-=-. For the case of resistive source (RS) and capacitive load (CL) impedances, the coefficient of s in the transfer function can be obtained as [8] b1 = RSC + RSCL + RC 2 + RCL. Efficient delay estimate... |

5 | Overshoot control for two coupled RLC interconnect - Yang, Brews - 1994 |

4 | Optimal Self-Damped Lossy Transmission Line Interconnections for Multichip Modules - Frye, Chen - 1992 |

3 | A General Methodology for Response and Delay - Kahng, Muddu - 1994 |

3 |
et al., \The Elmore Delay as a Bound for RC Trees with Generalized Input Signals
- Gupta
- 1995
(Show Context)
Citation Context ...off by as much as 50% from SPICE-computed delays for 50% threshold voltage, and the analytical ramp input model cannot be used to obtain threshold delay for various threshold voltages. The authors of =-=[5]-=- used Elmore delay as an upper bound on the 50% threshold delay for RC interconnection lines under arbitrary input waveforms. However, we find that Elmore delay is not at all close to SPICE-computed 5... |

3 |
Signal Delay in General RC
- Lin, Mead
- 1984
(Show Context)
Citation Context ...ay is TAD = TR 2 + b1 , a1 = TR 2 + TED (3) where TED is the Elmore delay for a step input (i.e., the first moment of the transfer function). Another definition of delay based on the formula given in =-=[10]-=- yields the same result of Equation (3) [9]. Group Delay Definition. The concept of group delay was initially defined for step input by Vlach et al. [18]. We now give a group delay definition for comp... |

3 |
AWESpice: A General Tool for the Accurate and Efficient
- Raghavan, Bracken, et al.
- 1992
(Show Context)
Citation Context ...bitrary interconnect structures, but impedance (Figure 1) can be obtained using ABCD parameters [1] as are computationally expensive. Faster methodsbased on moment matching techniques are proposed in =-=[12, 13, 14, 17]-=-, but are still too expen1 sive to be used during layout optimization. Thus, Elmore delay [2], a H(s) = h ZS first order approximation of delay understep input, is still the most widely cosh(θh)+ Z0 u... |

1 |
Horowitz,“TimingModels forMOS Circuits
- A
- 1984
(Show Context)
Citation Context ...S and load impedance ZT . By considering only one pole in the transfer function, i.e, approximating the denominator polynomial to only the first moment, the single pole response can be obtained as in =-=[4, 15]-=-. The single pole of the transfer function is equal to the inverse of the Elmore delay TED. Hence, the delay at arbitrary thresholds of the single pole response can be directly related to Elmore delay... |

1 |
Simple Expressions for Interconnect Delay and Input Transition Time”, manuscript
- Shirali
- 1995
(Show Context)
Citation Context ... write the threshold voltage corresponding to the rise-time TR in terms of interconnect and rise time parameters: V 0 Th2 Voltage Note that as t ! ∞, vout(t) tends to a final value of V0 as expected. =-=[16]-=- used a similar single-pole analysis to compute delay and transition times solving the above response equations by applying Newton-Raphson iteration. 4.1 Analytical Delay Model It turns out that using... |

1 |
Fast Approximationof The Transient Response of Lossy Transmission Line Trees
- Sriram, Kang
- 1993
(Show Context)
Citation Context ...bitrary interconnect structures, but impedance (Figure 1) can be obtained using ABCD parameters [1] as are computationally expensive. Faster methodsbased on moment matching techniques are proposed in =-=[12, 13, 14, 17]-=-, but are still too expen1 sive to be used during layout optimization. Thus, Elmore delay [2], a H(s) = h ZS first order approximation of delay understep input, is still the most widely cosh(θh)+ Z0 u... |

1 |
et al., “Group Delay as an Estimate of Delay in Logic
- Vlach
- 1991
(Show Context)
Citation Context ...inition of delay based on the formula given in [10] yields the same result of Equation (3) [9]. Group Delay Definition. The concept of group delay was initially defined for step input by Vlach et al. =-=[18]-=-. We now give a group delay definition for computing ramp input delay similar to that in [18], and show that it converges to the same analytical expression of Equation (3). Recall that group delay is ... |