## On-Chip Inductance Modeling and Analysis (2000)

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Venue: | Proc. of the ACM/IEEE Design Automation Conference |

Citations: | 24 - 2 self |

### BibTeX

@INPROCEEDINGS{Gala00on-chipinductance,

author = {Kaushik Gala and Vladimir Zolotov and Rajendran P and Brian Young and Junfeng Wang and David Blaauw},

title = {On-Chip Inductance Modeling and Analysis},

booktitle = {Proc. of the ACM/IEEE Design Automation Conference},

year = {2000},

pages = {63--68}

}

### Years of Citing Articles

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### Abstract

With operating frequencies approaching the gigahertz range, inductance is becoming an increasingly important consideration in the design and analysis of on-chip interconnect. We present an accurate technique for modeling and analyzing the effects of parasitic inductance on power grid noise, signal delay and crosstalk. We propose a detailed circuit model composed of interconnect resistance, inductance and distributed capacitance, device decoupling capacitances, quiescent activity in the grid, pad locations, and pad/package inductance which accurately determines current distribution and, hence, on-chip inductive effects, and proves superior to the traditional simplified loop inductance approach. The model uses partial inductances, computed using an analytical formula for a pair of parallel rectangular conductors spaced in any relative position. We present experimental results, obtained from simulations of industrial circuits, that show the importance of various model components while analyzing on-chip inductance. We also propose a simple sparsification technique to handle large, dense partial inductance matrices. 1

### Citations

108 |
Inductance calculations in a complex integrated circuit environment
- Ruehli
- 1972
(Show Context)
Citation Context ...implicity of the loop inductance model means it is faster to simulate, and can be used as a pre-layout estimation methodology. Alternative approaches use the Partial Equivalent Elements Circuit (PEEC)=-=[6]-=- method based on partial inductances, which can be defined for wire segments. The PEEC method can be used to construct a circuit model that does not require the predetermination of current loops. PEEC... |

52 |
Inductance Calculations: Working Formulas and Tables
- Grover
- 1973
(Show Context)
Citation Context ... formulation given in [8]. Next, the partial self and mutual inductances are obtained using formulae that are functions of the GMD, the conductor lengths and their relative spacing in the Z dimension =-=[9]-=-. An alternative formulation, which includes all 3 dimensions in the same expression, can also be used to compute the inductance values[10]. These analytic formulae are exact, under the assumption of ... |

33 | Layout Based Frequency Depended Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis,” DAC
- Krauter
- 1998
(Show Context)
Citation Context ...ult, since it requires the accurate modeling and simulation of the complete signal net and power grid topology. Traditional approaches to inductance analysis are based on simple loop inductance models=-=[2]-=-, [3], [4]. The loop inductance and resistance are extracted by defining ports at the driving gate, and then solving the current distribution for an RL model of the circuit using tools such as FastHen... |

28 | Generating Sparse Partial Inductance Matrices with Guaranteed Stability
- Krauter, Pileggi
- 1996
(Show Context)
Citation Context ... in indefinite matrices, which imply unstable systems. As an alternative to simple truncation, one approach associates each segment with a distributed current return path out to a shell of some radius=-=[11]-=-. Segments with spacing more than this radius are assumed to have no inductive coupling. However, this approach leads to complications in determining the global value of the shell radius. An extension... |

25 |
et al, “When are Transmission-Line Effects Important for On-Chip Interconnections
- Deutsch, Restle
- 1997
(Show Context)
Citation Context ...la, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw Motorola Inc., Austin TX 78729 Inductance effects in on-chip interconnect structures have become increasingly significant=-=[1]-=- due to longer metal interconnects, reductions in wire resistance (as a result of copper interconnects and wider upper-layer metal lines) and higher frequency operation. These effects are particularly... |

13 |
Including Inductive Effects in Interconnect Timing Analysis,” CICC
- Krauter
- 1999
(Show Context)
Citation Context ...d be dropped. Our experiments with this technique indicate that it can lead to huge inaccuracies, since the power grid provides an important return path for signal currents. Reduced-order models [14],=-=[15]-=- for the linear portion of the model can be combined with the gate models and simulated in SPICE. However, model order reduction algorithms such as PRIMA[16] require matrix inversion, which is expensi... |

4 |
et al, “Layout Techniques for Minimizing On-Chip Interconnect Self-Inductance,” DAC
- Massoud
- 1998
(Show Context)
Citation Context ... it requires the accurate modeling and simulation of the complete signal net and power grid topology. Traditional approaches to inductance analysis are based on simple loop inductance models[2], [3], =-=[4]-=-. The loop inductance and resistance are extracted by defining ports at the driving gate, and then solving the current distribution for an RL model of the circuit using tools such as FastHenry[5]. The... |

4 |
et al, “An Efficient Inductance Modeling for Onchip Interconnects,” CICC
- He
- 1999
(Show Context)
Citation Context ... segments. The PEEC method can be used to construct a circuit model that does not require the predetermination of current loops. PEEC models have been used to obtain more accurate current distribution=-=[7]-=-. However, such techniques have been applied to highly simplified structures like coplanar waveguides. In addition, they ignore important components that determine current paths, and hence lack accura... |

4 |
et al, “Return-Limited Inductances: A Practical Approach to On-Chip Inductance Extraction,” CICC
- Shepard
- 1999
(Show Context)
Citation Context ...er, this approach leads to complications in determining the global value of the shell radius. An extension of this work[12] uses a moment-based algorithm to compute the shell radius. A recent approach=-=[13]-=- introduces return-limited inductances for sparsification and the use of “halos” to limit the number of mutual inductances. However, a chief assumption requires that the mutual inductances between sig... |

4 |
et al, “PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm,” ICCAD
- Odabasioglu
- 1997
(Show Context)
Citation Context ...signal currents. Reduced-order models [14],[15] for the linear portion of the model can be combined with the gate models and simulated in SPICE. However, model order reduction algorithms such as PRIMA=-=[16]-=- require matrix inversion, which is expensive for the fully-dense matrix of our model. Also, they cannot handle time-varying current sources or non-linear devices, which we use to model the switching ... |

3 |
et al, “Exact Inductance Equations for Rectangular Conductors with Applications to More Complicated Geometries
- Hoer
- 1965
(Show Context)
Citation Context ...nductor lengths and their relative spacing in the Z dimension [9]. An alternative formulation, which includes all 3 dimensions in the same expression, can also be used to compute the inductance values=-=[10]-=-. These analytic formulae are exact, under the assumption of uniform current distribution. However, they ignore the skin effect and proximity effect within the conductor. For a rise-time of 100ps, the... |

3 |
et al, “IC Analyses Including Extracted Inductance Models,” DAC
- Beattie
- 1999
(Show Context)
Citation Context ...r grid be dropped. Our experiments with this technique indicate that it can lead to huge inaccuracies, since the power grid provides an important return path for signal currents. Reduced-order models =-=[14]-=-,[15] for the linear portion of the model can be combined with the gate models and simulated in SPICE. However, model order reduction algorithms such as PRIMA[16] require matrix inversion, which is ex... |

2 |
et al, “Mesh-Structured On-Chip Power/Ground: Design for Minimum Inductance and Characterization for Fast R
- Sinha
- 1999
(Show Context)
Citation Context ...since it requires the accurate modeling and simulation of the complete signal net and power grid topology. Traditional approaches to inductance analysis are based on simple loop inductance models[2], =-=[3]-=-, [4]. The loop inductance and resistance are extracted by defining ports at the driving gate, and then solving the current distribution for an RL model of the circuit using tools such as FastHenry[5]... |

2 |
et al, “FASTHENRY: A Multipole-Accelerated 3-D Inductance Extraction Program
- Kamon
- 1994
(Show Context)
Citation Context ...[3], [4]. The loop inductance and resistance are extracted by defining ports at the driving gate, and then solving the current distribution for an RL model of the circuit using tools such as FastHenry=-=[5]-=-. The extracted inductance and resistance are then combined with lumped capacitance to construct a netlist. While extracting the inductance, current distribution is determined solely by the resistance... |

2 |
et al, “Analysis and Design of TransmissionLine Structures by means of the Geometric Mean Distance
- Sinclair
- 1996
(Show Context)
Citation Context ...he two conductors. This is a function of the conductor widths, thicknesses and their spacing in the X and Y dimensions. The GMD formulation was derived by developing the integral formulation given in =-=[8]-=-. Next, the partial self and mutual inductances are obtained using formulae that are functions of the GMD, the conductor lengths and their relative spacing in the Z dimension [9]. An alternative formu... |

2 |
et al, “SPIE: Sparse Partial Inductance Extraction,” DAC
- He
- 1997
(Show Context)
Citation Context ...th spacing more than this radius are assumed to have no inductive coupling. However, this approach leads to complications in determining the global value of the shell radius. An extension of this work=-=[12]-=- uses a moment-based algorithm to compute the shell radius. A recent approach[13] introduces return-limited inductances for sparsification and the use of “halos” to limit the number of mutual inductan... |