DMCA
Minimum Energy CMOS Design with Dual Subthreshold Supply and Multiple Logic-Level Gates
| Citations: | 8 - 6 self |
BibTeX
@MISC{Kim_minimumenergy,
author = {Kyungseok Kim and Vishwani D. Agrawal},
title = {Minimum Energy CMOS Design with Dual Subthreshold Supply and Multiple Logic-Level Gates},
year = {}
}
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Abstract
Abstract—This paper presents a method for minimum energy digital CMOS circuit design using dual subthreshold supply voltages. Stringent energy budget and moderate speed requirements of some ultra low power systems may not be best satisfied just by scaling a single supply voltage. Optimized circuits with dual supply voltages provide an opportunity to resolve these demands. The delay penalty of a traditional level converter is unacceptably high when the voltages are in the subthreshold range. In the present work level converters are not used and special multiple logic-level gates are used only when, after accounting for their cost, they offer advantage. Starting from a lowest per cycle energy design whose single supply voltage is in the subthreshold range, a new mixed integer linear program (MILP) finds a second lower supply voltage optimally assigned to gates with time slack. The MILP accounts for the energy and delay characteristics of logic gates interfacing two different signal levels. New types of linearized AND and OR constraints are used in this MILP. We show energy saving up to 24.5 % over the best available designs of ISCAS’85 benchmark circuits. Keywords — Ultra-low power design, Subthreshold circuits, Dual voltage design, Mixed integer linear program.
Keyphrases
multiple logic-level gate dual subthreshold supply minimum energy cmos design single supply voltage subthreshold range available design keywords ultra-low power design logic gate dual supply voltage milp account benchmark circuit new mixed integer linear program present work level converter delay penalty different signal level mixed integer linear program dual subthreshold supply voltage subthreshold circuit cycle energy design supply voltage stringent energy budget new type ultra low power system time slack moderate speed requirement dual voltage design traditional level converter delay characteristic special multiple logic-level gate
