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... feature size [2]. Utilizing the time slack for dual Vdd is a well-known technique for a circuit operating with nominal Vdd for reducing the power consumption with small extra cost in physical design =-=[18]-=-, [19]. However, operation in the subthreshold voltage region has been long predicted and since verified [20]. Most previous works in subthreshold circuit design only used a single supply voltage scal...

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...ual Vdd design in the subthreshold regime. We use the HSPICE simulator [7] to size properly for reducing the delay of two ALCs in subthreshold region. Predictive Technology Model (PTM) for 90 nm CMOS =-=[23]-=- was used in the simulations. Table I shows the delay penalty of the two optimized ALCs in a range of 28∼ 60× INV(FO4) delay, where INV(FO4) is the delay of a standard inverter with fanout of four. Th...

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...re size [2]. Utilizing the time slack for dual Vdd is a well-known technique for a circuit operating with nominal Vdd for reducing the power consumption with small extra cost in physical design [18], =-=[19]-=-. However, operation in the subthreshold voltage region has been long predicted and since verified [20]. Most previous works in subthreshold circuit design only used a single supply voltage scaled dow...

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...lications. When we scale the power supply voltage (Vdd) below the device threshold voltage (Vth), the subthreshold current ever so slowly charges and discharges nodes for the circuit’s logic function =-=[20]-=-. The weak driving current limits the performance but minimum energy operation of the circuit is achieved with reduced dynamic and leakage power resulting in long battery life [11]. A successful subth...

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...ge power resulting in long battery life [11]. A successful subthreshold design is possible in clock ranges of low to medium frequencies for biomedical and micro-sensor network applications [8], [16], =-=[21]-=-. Ultra dynamic voltage scaling (UDVS) [3] can provide more opportunity to spread subthreshold circuit design in various applications by switching between a nominal voltage high performance mode and a...

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...l power supply constraints, MILP only chooses two supply voltages, given VDDH and optimal VDDL, then each gate in the circuit must be assigned to one of them from (11); we use a bin-packing technique =-=[1]-=-. Penalty condition tests the existence of a VDDH gate driven by at least one VDDL fan-in gate from (5) (Boolean Or) and (6) (Boolean AND). The nonlinear Boolean functions are expressed as linear cons...

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...c and leakage power resulting in long battery life [11]. A successful subthreshold design is possible in clock ranges of low to medium frequencies for biomedical and micro-sensor network applications =-=[8]-=-, [16], [21]. Ultra dynamic voltage scaling (UDVS) [3] can provide more opportunity to spread subthreshold circuit design in various applications by switching between a nominal voltage high performanc...

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...nce. Near-threshold operating circuit design is another choice to cover a wider range of system performances for applications with tolerable energy increase (∼2X) from Emin by scaling Vdd to near Vth =-=[5]-=-. Technology down-scaling improves the speed of a subthreshold circuit, but greater variability may adversely affect Emin for extremely small feature size [2]. Utilizing the time slack for dual Vdd is...

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...]. A successful subthreshold design is possible in clock ranges of low to medium frequencies for biomedical and micro-sensor network applications [8], [16], [21]. Ultra dynamic voltage scaling (UDVS) =-=[3]-=- can provide more opportunity to spread subthreshold circuit design in various applications by switching between a nominal voltage high performance mode and an energy efficient subthreshold mode accor...

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...unction of a gate with subthreshold supply voltage and Vlow is the lowest input voltage to keep 10% to 90% output voltage swing for a logic gate when VDDH is predetermined. The timing constraints are =-=[14]-=-: Ti ≥ Tj + ∑ tdi,v · Xi,v + ∑ v∈V v∈VL tdoi,v · Pi,v ∀i ∈ all gates, ∀j ∈ all fanin gates of gate i (2) (3) Ti ≤ Tc ∀i ∈ all primary output gates (4) Penalty condition: ∑ Xj,v ≤ Ni · Fi,v j ∀j ∈ all ...

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...ates with time slack. This gives more power saving than CVS. We apply the dual voltage technique to subthreshold (b) Pass gate (PG) level converter. Fig. 2. Two traditional level converter schematics =-=[13]-=-. supply combinational circuits. To maximize energy saving from the time slack, a level converter is still considered essential. In Figure 2, two traditional ALCs, a differential cascode voltage switc...

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... (number of gates vs. slack) for minimum energy per cycle c880; slacks obtained by static timing analysis using gate delays for PTM 90nm CMOS. can be provided by a voltage scalable DC to DC converter =-=[15]-=-. We also assume that combinational benchmark circuits have no restriction for primary output voltage level either of VDDH or VDDL. In reality, level shifting flip-flops (LCFF) [18] can be placed at l...

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...penalty of the two optimized ALCs in a range of 28∼ 60× INV(FO4) delay, where INV(FO4) is the delay of a standard inverter with fanout of four. The normal ALC delay is considered as 2× INV(FO4) delay =-=[4]-=- for a nominal supply voltage. A low voltage microprocessor has ∼ 400× INV(FO4) delay for a single pipeline stage. The microprocessor operating in subthreshold region would prefer shallow pipeline to ...

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... dual voltage design for low voltage circuits. The dual voltage technique for a nominal voltage circuit is mainly applied for dynamic power saving, while leakage power saving is considered negligible =-=[12]-=-. V. Conclusion and Future Work This paper presents dual voltage design in the subthreshold regime. Level converters are eliminated and special multiple logic-level gates are used instead. This approa...

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...∼2X) from Emin by scaling Vdd to near Vth [5]. Technology down-scaling improves the speed of a subthreshold circuit, but greater variability may adversely affect Emin for extremely small feature size =-=[2]-=-. Utilizing the time slack for dual Vdd is a well-known technique for a circuit operating with nominal Vdd for reducing the power consumption with small extra cost in physical design [18], [19]. Howev...

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...zed circuits show energy saving of 14.0% on an average, even it includes the energy savings of path balanced circuits. Figure 5 shows the gate slack distributions obtained from static timing analysis =-=[9]-=- of the single Vdd and dual Vdd designs of c880. Clearly, it is the large number of gates with large slack in the single Vdd design that allows many low Vdd assignments. The energy saving from dual vo...

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...nce verified [20]. Most previous works in subthreshold circuit design only used a single supply voltage scaled down to reduce the energy consumption without considering the time slack. The authors of =-=[10]-=- derived a MILP algorithm to minimize the energy consumption of a subthreshold logic circuit using dual Vdd. Their work limits full use of the time slack by topological constraints considering multipl...

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... for a single pipeline stage. The microprocessor operating in subthreshold region would prefer shallow pipeline to mitigate variability and a 40× INV(FO4) delay is considered as a typical design case =-=[17]-=-. To reduce the delay penalty of level converting, we need to investigate alternative apKim, Minimum Energy CMOS Design with Dual ...TABLE I Delays of two optimal sized ALCs with a single INV load at...

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...it’s logic function [20]. The weak driving current limits the performance but minimum energy operation of the circuit is achieved with reduced dynamic and leakage power resulting in long battery life =-=[11]-=-. A successful subthreshold design is possible in clock ranges of low to medium frequencies for biomedical and micro-sensor network applications [8], [16], [21]. Ultra dynamic voltage scaling (UDVS) [...

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... gates on non-critical paths. With such delay characteristic, the delay overhead of the ALC is more critical for implementing a dual Vdd design in the subthreshold regime. We use the HSPICE simulator =-=[7]-=- to size properly for reducing the delay of two ALCs in subthreshold region. Predictive Technology Model (PTM) for 90 nm CMOS [23] was used in the simulations. Table I shows the delay penalty of the t...

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...]. A successful subthreshold design is possible in clock ranges of low to medium frequencies for biomedical and micro-sensor network applications [8], [16], [21]. Ultra dynamic voltage scaling (UDVS) =-=[3]-=- can provide more opportunity to spread subthreshold circuit design in various applications by switching between a nominal voltage high performance mode and an energy efficient subthreshold mode accor...