## Minimum Energy CMOS Design with Dual Subthreshold Supply and Multiple Logic-Level Gates

Citations: | 8 - 6 self |

### BibTeX

@MISC{Kim_minimumenergy,

author = {Kyungseok Kim and Vishwani D. Agrawal},

title = {Minimum Energy CMOS Design with Dual Subthreshold Supply and Multiple Logic-Level Gates},

year = {}

}

### OpenURL

### Abstract

Abstract—This paper presents a method for minimum energy digital CMOS circuit design using dual subthreshold supply voltages. Stringent energy budget and moderate speed requirements of some ultra low power systems may not be best satisfied just by scaling a single supply voltage. Optimized circuits with dual supply voltages provide an opportunity to resolve these demands. The delay penalty of a traditional level converter is unacceptably high when the voltages are in the subthreshold range. In the present work level converters are not used and special multiple logic-level gates are used only when, after accounting for their cost, they offer advantage. Starting from a lowest per cycle energy design whose single supply voltage is in the subthreshold range, a new mixed integer linear program (MILP) finds a second lower supply voltage optimally assigned to gates with time slack. The MILP accounts for the energy and delay characteristics of logic gates interfacing two different signal levels. New types of linearized AND and OR constraints are used in this MILP. We show energy saving up to 24.5 % over the best available designs of ISCAS’85 benchmark circuits. Keywords — Ultra-low power design, Subthreshold circuits, Dual voltage design, Mixed integer linear program.

### Citations

141 |
Clustered Voltage Scaling Technique for LowPower
- Usami, al
- 1995
(Show Context)
Citation Context ... feature size [2]. Utilizing the time slack for dual Vdd is a well-known technique for a circuit operating with nominal Vdd for reducing the power consumption with small extra cost in physical design =-=[18]-=-, [19]. However, operation in the subthreshold voltage region has been long predicted and since verified [20]. Most previous works in subthreshold circuit design only used a single supply voltage scal... |

140 |
New generation of predictive technology model for sub-45nm design exploration
- Zhao, Cao
- 2006
(Show Context)
Citation Context ...ual Vdd design in the subthreshold regime. We use the HSPICE simulator [7] to size properly for reducing the delay of two ALCs in subthreshold region. Predictive Technology Model (PTM) for 90 nm CMOS =-=[23]-=- was used in the simulations. Table I shows the delay penalty of the two optimized ALCs in a range of 28∼ 60× INV(FO4) delay, where INV(FO4) is the delay of a standard inverter with fanout of four. Th... |

51 |
Automated low-power technique exploiting multiple supply voltages applied to a media processor
- Usami, Nogami, et al.
- 1997
(Show Context)
Citation Context ...re size [2]. Utilizing the time slack for dual Vdd is a well-known technique for a circuit operating with nominal Vdd for reducing the power consumption with small extra cost in physical design [18], =-=[19]-=-. However, operation in the subthreshold voltage region has been long predicted and since verified [20]. Most previous works in subthreshold circuit design only used a single supply voltage scaled dow... |

36 |
Subthreshold Design for Ultra Low-Power Systems
- Wang, Clhoun, et al.
- 2006
(Show Context)
Citation Context ...lications. When we scale the power supply voltage (Vdd) below the device threshold voltage (Vth), the subthreshold current ever so slowly charges and discharges nodes for the circuit’s logic function =-=[20]-=-. The weak driving current limits the performance but minimum energy operation of the circuit is achieved with reduced dynamic and leakage power resulting in long battery life [11]. A successful subth... |

35 |
A 180mV FFT Processor Using Subthreshold Circuit Techniques," ISSCC
- Wang, Chandrakasan
- 2004
(Show Context)
Citation Context ...ge power resulting in long battery life [11]. A successful subthreshold design is possible in clock ranges of low to medium frequencies for biomedical and micro-sensor network applications [8], [16], =-=[21]-=-. Ultra dynamic voltage scaling (UDVS) [3] can provide more opportunity to spread subthreshold circuit design in various applications by switching between a nominal voltage high performance mode and a... |

34 | Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
- Anis, Areibi, et al.
(Show Context)
Citation Context ...l power supply constraints, MILP only chooses two supply voltages, given VDDH and optimal VDDL, then each gate in the circuit must be assigned to one of them from (11); we use a bin-packing technique =-=[1]-=-. Penalty condition tests the existence of a VDDH gate driven by at least one VDDL fan-in gate from (5) (Boolean Or) and (6) (Boolean AND). The nonlinear Boolean functions are expressed as linear cons... |

30 |
Ultra-low-power dlms adaptive filter for hearing aid applications
- Kim, Soeleman, et al.
- 2003
(Show Context)
Citation Context ...c and leakage power resulting in long battery life [11]. A successful subthreshold design is possible in clock ranges of low to medium frequencies for biomedical and micro-sensor network applications =-=[8]-=-, [16], [21]. Ultra dynamic voltage scaling (UDVS) [3] can provide more opportunity to spread subthreshold circuit design in various applications by switching between a nominal voltage high performanc... |

28 |
Near-threshold computing: Reclaiming Moore’s law through energy efficient integrated circuits
- Dreslinski, Wieckowski, et al.
- 2010
(Show Context)
Citation Context ...nce. Near-threshold operating circuit design is another choice to cover a wider range of system performances for applications with tolerable energy increase (∼2X) from Emin by scaling Vdd to near Vth =-=[5]-=-. Technology down-scaling improves the speed of a subthreshold circuit, but greater variability may adversely affect Emin for extremely small feature size [2]. Utilizing the time slack for dual Vdd is... |

22 |
Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-Threshold Operation and Local Voltage Dithering
- Calhoun, Chandrakasan
- 2006
(Show Context)
Citation Context ...]. A successful subthreshold design is possible in clock ranges of low to medium frequencies for biomedical and micro-sensor network applications [8], [16], [21]. Ultra dynamic voltage scaling (UDVS) =-=[3]-=- can provide more opportunity to spread subthreshold circuit design in various applications by switching between a nominal voltage high performance mode and an energy efficient subthreshold mode accor... |

18 | Minimum dynamic power CMOS circuit design by a reduced constraint set linear program
- Raja, Agrawal, et al.
- 2003
(Show Context)
Citation Context ...unction of a gate with subthreshold supply voltage and Vlow is the lowest input voltage to keep 10% to 90% output voltage swing for a logic gate when VDDH is predetermined. The timing constraints are =-=[14]-=-: Ti ≥ Tj + ∑ tdi,v · Xi,v + ∑ v∈V v∈VL tdoi,v · Pi,v ∀i ∈ all gates, ∀j ∈ all fanin gates of gate i (2) (3) Ti ≤ Tc ∀i ∈ all primary output gates (4) Penalty condition: ∑ Xj,v ≤ Ni · Fi,v j ∀j ∈ all ... |

15 |
High performance level conversion for dual VDD design
- Kulkarni, Sylvester
- 2004
(Show Context)
Citation Context ...ates with time slack. This gives more power saving than CVS. We apply the dual voltage technique to subthreshold (b) Pass gate (PG) level converter. Fig. 2. Two traditional level converter schematics =-=[13]-=-. supply combinational circuits. To maximize energy saving from the time slack, a level converter is still considered essential. In Figure 2, two traditional ALCs, a differential cascode voltage switc... |

14 |
Voltage scalable switched capacitor DC-DC converter for ultra-low-power on-chip applications
- Ramadass, Chandrakasan
(Show Context)
Citation Context ... (number of gates vs. slack) for minimum energy per cycle c880; slacks obtained by static timing analysis using gate delays for PTM 90nm CMOS. can be provided by a voltage scalable DC to DC converter =-=[15]-=-. We also assume that combinational benchmark circuits have no restriction for primary output voltage level either of VDDH or VDDL. In reality, level shifting flip-flops (LCFF) [18] can be placed at l... |

9 |
Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages
- Diril, Dhillon
- 2005
(Show Context)
Citation Context ...penalty of the two optimized ALCs in a range of 28∼ 60× INV(FO4) delay, where INV(FO4) is the delay of a standard inverter with fanout of four. The normal ALC delay is considered as 2× INV(FO4) delay =-=[4]-=- for a nominal supply voltage. A low voltage microprocessor has ∼ 400× INV(FO4) delay for a single pipeline stage. The microprocessor operating in subthreshold region would prefer shallow pipeline to ... |

8 |
A New Algorithm for Improved Vdd Assignment
- Kulkarni, Srivastava, et al.
- 2004
(Show Context)
Citation Context ... dual voltage design for low voltage circuits. The dual voltage technique for a nominal voltage circuit is mainly applied for dynamic power saving, while leakage power saving is considered negligible =-=[12]-=-. V. Conclusion and Future Work This paper presents dual voltage design in the subthreshold regime. Level converters are eliminated and special multiple logic-level gates are used instead. This approa... |

6 |
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
- Bol, Kamel, et al.
- 2009
(Show Context)
Citation Context ...∼2X) from Emin by scaling Vdd to near Vth [5]. Technology down-scaling improves the speed of a subthreshold circuit, but greater variability may adversely affect Emin for extremely small feature size =-=[2]-=-. Utilizing the time slack for dual Vdd is a well-known technique for a circuit operating with nominal Vdd for reducing the power consumption with small extra cost in physical design [18], [19]. Howev... |

6 |
Dual voltage design for minimum energy using gate slack
- Kim, Agrawal
- 2011
(Show Context)
Citation Context ...zed circuits show energy saving of 14.0% on an average, even it includes the energy savings of path balanced circuits. Figure 5 shows the gate slack distributions obtained from static timing analysis =-=[9]-=- of the single Vdd and dual Vdd designs of c880. Clearly, it is the large number of gates with large slack in the single Vdd design that allows many low Vdd assignments. The energy saving from dual vo... |

6 | True Minimum Energy Design Using Dual Below-Threshold Supply Voltages
- Kim, Agrawal
- 2011
(Show Context)
Citation Context ...nce verified [20]. Most previous works in subthreshold circuit design only used a single supply voltage scaled down to reduce the energy consumption without considering the time slack. The authors of =-=[10]-=- derived a MILP algorithm to minimize the energy consumption of a subthreshold logic circuit using dual Vdd. Their work limits full use of the time slack by topological constraints considering multipl... |

5 |
Optimal Technology Selection for Minimizing Energy and Variability
- Seok, Sylvester, et al.
- 2008
(Show Context)
Citation Context ... for a single pipeline stage. The microprocessor operating in subthreshold region would prefer shallow pipeline to mitigate variability and a 40× INV(FO4) delay is considered as a typical design case =-=[17]-=-. To reduce the delay penalty of level converting, we need to investigate alternative apKim, Minimum Energy CMOS Design with Dual ...TABLE I Delays of two optimal sized ALCs with a single INV load at... |

3 | A Tutorial on Battery Simulation - Matching Power Source to Electronic System
- Kulkarni, Agrawal
- 2010
(Show Context)
Citation Context ...it’s logic function [20]. The weak driving current limits the performance but minimum energy operation of the circuit is achieved with reduced dynamic and leakage power resulting in long battery life =-=[11]-=-. A successful subthreshold design is possible in clock ranges of low to medium frequencies for biomedical and micro-sensor network applications [8], [16], [21]. Ultra dynamic voltage scaling (UDVS) [... |

2 |
User Guide: Simulation and Analysis
- HSPICE
(Show Context)
Citation Context ... gates on non-critical paths. With such delay characteristic, the delay overhead of the ALC is more critical for implementing a dual Vdd design in the subthreshold regime. We use the HSPICE simulator =-=[7]-=- to size properly for reducing the delay of two ALCs in subthreshold region. Predictive Technology Model (PTM) for 90 nm CMOS [23] was used in the simulations. Table I shows the delay penalty of the t... |

1 |
Scaling (UDVS) Using Sub-Threshold Operation and Local Voltage Dithering
- Chandrakasan
- 2006
(Show Context)
Citation Context ...]. A successful subthreshold design is possible in clock ranges of low to medium frequencies for biomedical and micro-sensor network applications [8], [16], [21]. Ultra dynamic voltage scaling (UDVS) =-=[3]-=- can provide more opportunity to spread subthreshold circuit design in various applications by switching between a nominal voltage high performance mode and an energy efficient subthreshold mode accor... |