DMCA
Dual Voltage Design for Minimum Energy Using
BibTeX
@MISC{Slack_dualvoltage,
author = {Gate Slack and Kyungseok Kim and Vishwani D. Agrawal},
title = {Dual Voltage Design for Minimum Energy Using},
year = {}
}
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Abstract
Abstract—This paper presents a new slack-time based algorithm for dual Vdd design to achieve maximum energy saving. Although a global optimum is sought computation time is kept low. The slack of a gate is defined as the difference between the critical path delay for the circuit and the delay of the longest path through that gate. A linear-time algorithm is used for computing slacks for all gates of the circuit. Positive non-zero slack gates are classified into two groups, one in which all gates can be unconditionally assigned low voltage and the other where only a selected subset can be assigned low voltage without violating the positive non-zero slack requirement. Multiple voltage boundaries are given special consideration. The overall complexity of this power optimization algorithm is linear in number of gates as compared to a previously published exponential-time exact algorithm using mixed integer linear program (MILP). We apply the new algorithm to optimize ISCAS’85 benchmark circuits and compare the results with those from MILP. We avoid the use of level converters at multiple voltage boundaries. Energy savings from the new slack-time based algorithm is very closed to those from MILP. For c880, the energy saving is 22 % for subthreshold voltage operation and 50 % for nominal operation in PTM CMOS 90nm. For c2670 nominal voltage design, time of dual voltage optimization is reduced 44X compared to the MILP method. This new algorithm is beneficial for a large circuits with many large positive slack paths that would require enormous time for optimization by the MILP approach. I.
Keyphrases
dual voltage design minimum energy using new algorithm new slack-time multiple voltage boundary low voltage energy saving power optimization algorithm c2670 nominal voltage design overall complexity milp method dual voltage optimization special consideration maximum energy many large positive slack path dual vdd design ptm cmos positive non-zero slack gate benchmark circuit level converter exponential-time exact algorithm linear-time algorithm positive non-zero slack requirement mixed integer linear program global optimum large circuit subthreshold voltage operation critical path delay milp approach computation time nominal operation enormous time
