A 285-MHz Pipelined MAP Decoder in 0.18- m CMOS
BibTeX
@MISC{Lee_a285-mhz,
author = {Seok-jun Lee and Naresh R. Shanbhag and Senior Member and Andrew C. Singer},
title = {A 285-MHz Pipelined MAP Decoder in 0.18- m CMOS},
year = {}
}
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Abstract
Abstract—Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP) decoder IC. The 8.7-mm2 IC is implemented in a 1.8-V 0.18- m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a block-interleaved pipelined architecture, which enables the pipelining of the add-compare-select kernels. Measured results indicate that a turbo decoder based on the presented MAP decoder core can achieve: 1) a decoding throughput of 27.6 Mb/s with an energy-efficiency of 2.36 nJ/b/iter; 2) the highest clock frequency compared to existing 0.18- m designs with the smallest area; and 3) comparable throughput with an area reduction of 3-4 3 with reference to a look-ahead based high-speed design (Radix-4 design), and a parallel architecture. Index Terms—CMOS, iterative processing, maximum a posteriori probability (MAP) decoder, pipeline, turbo decoder, turbo equalizer. I.
