## Automatic Verification of Pipelined Microprocessor Control (1994)

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Citations: | 277 - 6 self |

### BibTeX

@INPROCEEDINGS{Burch94automaticverification,

author = {Jerry Burch and David Dill},

title = {Automatic Verification of Pipelined Microprocessor Control},

booktitle = {},

year = {1994},

pages = {68--80},

publisher = {Springer-Verlag}

}

### Years of Citing Articles

### OpenURL

### Abstract

We describe a technique for verifying the control logic of pipelined microprocessors. It handles more complicated designs, and requires less human intervention, than existing methods. The technique automaticMly compares a pipelined implementation to an architectural description. The CPU time needed for verification is independent of the data path width, the register file size, and the number of ALU operations.

### Citations

4269 |
Computer architecture: a quantitative approach
- Hennessy, Patterson
- 2002
(Show Context)
Citation Context ...cing these issues more efficiently. 4 Experimental Results In this section, we describe empirical results for applying our verification method to a pipelined ALU [5] and a subset of the DLX processor =-=[14]-=-. 4.1 Pipelined ALU The 3-stage pipelined ALU we considered (figure 3) has been used as a benchmark for BDD-based verification methods [3, 4, 5, 6]. A natural way to compare the performance of these m... |

666 | Model checking and abstraction
- Clarke, Grumberg, et al.
- 1994
(Show Context)
Citation Context ...hod to a pipelined ALU [5] and a subset of the DLX processor [14]. 4.1 Pipelined ALU The 3-stage pipelined ALU we considered (figure 3) has been used as a benchmark for BDD-based verification methods =-=[3, 4, 5, 6]-=-. A natural way to compare the performance of these methods is to see how the CPU time needed for verification grows as the pipeline is increased in size by (for example) increasing its datapath width... |

468 | Efficient implementation of a bdd package
- Brace, Rudell, et al.
- 1990
(Show Context)
Citation Context ...ing them. The validity problem for this logic is decidable. In practice, the complexity is dominated by handling Boolean connectives, just as with representations for propositional logic such as BDDs =-=[2]-=-. However, the additional expressiveness of our logic allows verification problems to be described at a higher level of abstraction than with propositional logic. As a result, there is a substantial r... |

412 | Simplification by Cooperating Decision Procedures
- Nelson, Oppen
- 1979
(Show Context)
Citation Context ...c we use to encode the formulas. 3.1 Uninterpreted Functions with Equality Many quantifier-free logics that include uninterpreted functions and equality have been studied. Unlike most of those logics =-=[18, 21]-=-, ours does not include addition or any arithmetical relations. For our application of verifying microprocessor control, there does not appear to be any need to have arithmetic built into the logic (a... |

180 |
Sequential Circuit Verification Using Symbolic Model Checking
- Burch, Clarke, et al.
- 1990
(Show Context)
Citation Context ...ill experimenting with ideas for balancing these issues more efficiently. 4 Experimental Results In this section, we describe empirical results for applying our verification method to a pipelined ALU =-=[5]-=- and a subset of the DLX processor [14]. 4.1 Pipelined ALU The 3-stage pipelined ALU we considered (figure 3) has been used as a benchmark for BDD-based verification methods [3, 4, 5, 6]. A natural wa... |

71 |
Representing circuits more efficiently in symbolic model checking
- Burch, Clarke, et al.
- 1991
(Show Context)
Citation Context ...hod to a pipelined ALU [5] and a subset of the DLX processor [14]. 4.1 Pipelined ALU The 3-stage pipelined ALU we considered (figure 3) has been used as a benchmark for BDD-based verification methods =-=[3, 4, 5, 6]-=-. A natural way to compare the performance of these methods is to see how the CPU time needed for verification grows as the pipeline is increased in size by (for example) increasing its datapath width... |

69 |
A practical decision procedure for arithmetic with function symbols
- Shostak
- 1979
(Show Context)
Citation Context ...c we use to encode the formulas. 3.1 Uninterpreted Functions with Equality Many quantifier-free logics that include uninterpreted functions and equality have been studied. Unlike most of those logics =-=[18, 21]-=-, ours does not include addition or any arithmetical relations. For our application of verifying microprocessor control, there does not appear to be any need to have arithmetic built into the logic (a... |

67 |
FM8501: A Verified Microprocessor
- Hunt
- 1985
(Show Context)
Citation Context ...e labor, and provide information to help pinpoint design errors. The best-known examples of formally verified processors have been extremely simple processor designs, which were generally unpipelined =-=[7, 8, 15, 16]-=-. The verification methods used rely on theorem-provers that require a great deal of very skilled human guidance (the practical unit of for measuring labor in these studies seems to be the person-mont... |

57 |
Formal verification of a pipelined microprocessor
- Srivas, Bickford
- 1990
(Show Context)
Citation Context ...n are in a proper relationship, but that relationship is not necessarily easy to define. Recently, there have been successful efforts to verify pipelined processors using human-guided theorem-provers =-=[11, 19, 20, 22]-=-. However, in all of these cases, either the processor was extremely simple or a large amount of labor was required. Although the examples we have attacked are still much simpler than current high-per... |

46 |
Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation
- Bryant, Beatty, et al.
- 1991
(Show Context)
Citation Context ...hod to a pipelined ALU [5] and a subset of the DLX processor [14]. 4.1 Pipelined ALU The 3-stage pipelined ALU we considered (figure 3) has been used as a benchmark for BDD-based verification methods =-=[3, 4, 5, 6]-=-. A natural way to compare the performance of these methods is to see how the CPU time needed for verification grows as the pipeline is increased in size by (for example) increasing its datapath width... |

43 | Microprocessor Verification in PVS: A Methodology and Simple Example
- CYRLUK
- 1993
(Show Context)
Citation Context ...n are in a proper relationship, but that relationship is not necessarily easy to define. Recently, there have been successful efforts to verify pipelined processors using human-guided theorem-provers =-=[11, 19, 20, 22]-=-. However, in all of these cases, either the processor was extremely simple or a large amount of labor was required. Although the examples we have attacked are still much simpler than current high-per... |

32 |
A Methodology for Formal Hardware Verification with Application to Microprocessors
- Beatty
- 1993
(Show Context)
Citation Context ...). Furthermore, the processor implementations that were verified were so simple that they were able to avoid central problems such as control complexity. There are more recent verification techniques =-=[1, 17]-=- that are much more automatic, but they have not been demonstrated on pipelined processors. The verification of modern processors poses a special problem. The natural specification of a processor is t... |

17 |
Proving a computer correct in higher order logic
- Joyce, Birtwistle, et al.
- 1986
(Show Context)
Citation Context ...e labor, and provide information to help pinpoint design errors. The best-known examples of formally verified processors have been extremely simple processor designs, which were generally unpipelined =-=[7, 8, 15, 16]-=-. The verification methods used rely on theorem-provers that require a great deal of very skilled human guidance (the practical unit of for measuring labor in these studies seems to be the person-mont... |

8 |
Occam in the specification and verification of microprocessors
- Roscoe
- 1992
(Show Context)
Citation Context ...n are in a proper relationship, but that relationship is not necessarily easy to define. Recently, there have been successful efforts to verify pipelined processors using human-guided theorem-provers =-=[11, 19, 20, 22]-=-. However, in all of these cases, either the processor was extremely simple or a large amount of labor was required. Although the examples we have attacked are still much simpler than current high-per... |

6 |
Verification of processor-like circuits
- Langevin, Cerny
- 1991
(Show Context)
Citation Context ...). Furthermore, the processor implementations that were verified were so simple that they were able to avoid central problems such as control complexity. There are more recent verification techniques =-=[1, 17]-=- that are much more automatic, but they have not been demonstrated on pipelined processors. The verification of modern processors poses a special problem. The natural specification of a processor is t... |

4 |
Using transformations and verification in circuit design
- Saxe, Garland, et al.
- 1991
(Show Context)
Citation Context |

3 |
Designing a computer as a microprocessor: Experience and lessons from the MIPS 4000. A lecture at the Symposium on Integrated Systems
- Hennessy
- 1993
(Show Context)
Citation Context ...actor in design time. For example, each month of additional design time of the MIPS 4000 processor was estimated to cost $3-$8 million, and 27% of the design time was spent in "verification and t=-=est" [13]-=-. We believe that formal verification methods could eventually have a significant economic impact on microprocessor designs by providing faster methods for catching design errors, resulting in fewer d... |

1 |
A proof of correctness of the Viper microprocessors: The first level
- Cobh
- 1988
(Show Context)
Citation Context ...e labor, and provide information to help pinpoint design errors. The best-known examples of formally verified processors have been extremely simple processor designs, which were generally unpipelined =-=[7, 8, 15, 16]-=-. The verification methods used rely on theorem-provers that require a great deal of very skilled human guidance (the practical unit of for measuring labor in these studies seems to be the person-mont... |

1 |
Correctness properties of the Viper block model: The second level
- Cobh
- 1989
(Show Context)
Citation Context |

1 |
Automated high-level verification against docked algorithmic specifications
- Cotella
- 1992
(Show Context)
Citation Context ...e CPU time needed for verification. Cordia has also observed that uninterpreted functions and constants can be used to abstract away from the details of datapaths, in order to focus on control issues =-=[9, 10]-=-. He has a program for analyzing logical expressions which he has used for verifying a non-pipelined processor and a prefetch circuit. Although the details are not presented, his analysis procedure ap... |

1 | Also published as University of Cambridge Computer Lab- oratory Technical Report - Corella - 1989 |

1 | Occam in the specification and verification of microprocessors - Syst - 1979 |

1 | Philosophical Transactions of the Royal Society of London, Series A: Physical Sci- ences and Engineering - Saxe, Garland, et al. - 1992 |