## Synthesis of Timed Asynchronous Circuits (1993)

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Venue: | IEEE Transactions on VLSI Systems |

Citations: | 86 - 16 self |

### BibTeX

@ARTICLE{Myers93synthesisof,

author = {Chris Myers and Teresa H. -Y. Meng},

title = {Synthesis of Timed Asynchronous Circuits},

journal = {IEEE Transactions on VLSI Systems},

year = {1993},

volume = {1},

pages = {106--119}

}

### Years of Citing Articles

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### Abstract

In this paper we present a synthesis method that utilizes timing constraints to generate timed asynchronous circuits. By unfolding the cyclic graph specification of an asynchronous circuit into an infinite acyclic graph, we are able to use efficient algorithms to analyze the given timing constraints. We derive a sufficient condition for the removal of redundancy in the specification. Based on this condition, we only need to analyze a finite subgraph of the infinite acyclic graph for derivation of a correct implementation. To the reduced specification, we apply a systematic synthesis procedure that further optimizes the implementation based on the timing constraints. Using realistic circuit examples, we demonstrate that the resulting timed implementation can be significantly reduced in complexity from its speed-independent counterpart while remaining hazard-free under the given timing constraints.

### Citations

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Citation Context ... compactly represented using an event-rule (ER) schema. 2.1.1 Events An event is defined as " : : : an action which one can choose to regard as indivisible---it either has happened or has not : :=-= : " [19]. In circu-=-its, events are transitions of signals from one value to another. There are two transitions associated with each signal s in a specification, namely, s " where " denotes that the signal s is... |

204 |
Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications
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Citation Context ... Reduced State Graph In order to generate a circuit implementation, many methodologies transform a higher-level specification into a state graph so that Boolean minimization techniques can be applied =-=[2]-=- [3]. Essentially, a state graph is a graph in which the vertices are bitvectors and the arcs are signal transitions. Each bitvector specifies the binary value of every signal in the system when the s... |

164 | Asynchronous Sequential Switching Circuits - Unger - 1969 |

163 |
Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits
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Citation Context ... a result, our timed circuits retain the same behavior with less circuit complexity than earlier implementations. Many methodologies have been proposed for the synthesis of speed-independent circuits =-=[1]-=- [2] [3] [4]. Speed-independent circuits are very robust since they are guaranteed to work independent of the delays associated with their gates, but they can be overly conservative when timing constr... |

143 | Performance Analysis and Optimization of Asynchronous Circuits
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Citation Context ...b) Figure 2: (a) Schematic symbols for a generalized C-element. The first is the Muller C-element; the second is a set/reset flipflop; and the implementation of the third is given in (b) (Courtesy of =-=[3]-=-). The degree of complexity reduction in a timed circuit compared to a speed-independent one is dependent on the amount of concurrency in the specification. While this reduction of circuit complexity ... |

82 |
P.J.Hazewindus, “The Design of an Asynchronous Microprocessor,” Advanced research
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Citation Context ...h speed-independent circuits, while using the timing constraints to reduce the circuit complexity. In one practical memory interface [6] which was designed for use with an asynchronous microprocessor =-=[7]-=-, we were able to reduce the circuit complexity by 50 percent using very conservative timing constraints. This paper contains five sections. In section 2, we describe the specification language and th... |

77 | Algorithms for Synthesis of Hazard-Free Asynchronous Circuits
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Citation Context ...2-DJ-205. The authors are with the Department of Electrical Engineering, Stanford University, Stanford, CA 94305. Methods have been proposed to use timing constraints to synthesize timed circuits [9] =-=[10]-=-; however, most techniques apply timing constraints after synthesis only to verify that hazards do not exist. If hazards are detected, delay elements are added to avoid them, degrading the performance... |

75 |
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Citation Context ...ch context signals to use to optimally solve all conflicts constitutes a covering problem, which is solved by treating the table of conflict problems and possible solutions as a prime implicant table =-=[22]-=-. Thus, for each transition, a prime implicant table is solved using the procedure outlined in Algorithm 3.6. The function Choose essential rows determines if a problem has only one possible solution.... |

66 |
Algorithms for Interface Timing Verification
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Citation Context ...sary to determine the difference in the possible firing times between two transitions in a circuit specification. Recently, polynomial time algorithms have been developed by Vanbekbergen [1] and Dill =-=[2]-=- to determine this value for acyclic graphs. To apply these algorithms to circuit synthesis, these results must be expanded to handle cyclic specifications. One approach to this problem is to unfold t... |

64 | Automatic Synthesis of Asynchronous Circuits from HighLevel Specifications - Meng, Brodersen, et al. - 1989 |

55 |
Synthesis of asynchronous state machines using a local clock
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Citation Context ...uts in response to changes of outputs. Inputs from a synchronous circuit often do not satisfy this restriction. In order to address this problem, fundamental mode synthesis methods have been used [5] =-=[6]-=- [7] [8], which assume the environment will wait long enough for the circuit to stabilize before inputs are changed. Timing analysis must be performed after synthesis, and appropriate delays may need ... |

55 | The Post Office experience: Designing a large asynchronous chip
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- 1993
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Citation Context ...esponse to changes of outputs. Inputs from a synchronous circuit often do not satisfy this restriction. In order to address this problem, fundamental mode synthesis methods have been used [5] [6] [7] =-=[8]-=-, which assume the environment will wait long enough for the circuit to stabilize before inputs are changed. Timing analysis must be performed after synthesis, and appropriate delays may need to be ad... |

40 | Synthesis of 3D asynchronous state machines
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(Show Context)
Citation Context ...in response to changes of outputs. Inputs from a synchronous circuit often do not satisfy this restriction. In order to address this problem, fundamental mode synthesis methods have been used [5] [6] =-=[7]-=- [8], which assume the environment will wait long enough for the circuit to stabilize before inputs are changed. Timing analysis must be performed after synthesis, and appropriate delays may need to b... |

34 | Practical Asynchronous Controller Design
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Citation Context ...a synchronous processor and DRAM array is presented to illustrate a design that cannot be done speed-independently. Circuit complexity is also reduced as compared to previous fundamental mode designs =-=[13]-=- [7]. This paper contains five sections. Section 2 describes our specification language and timing analysis algorithm. Section 3 discusses our synthesis procedure. Section 4 presents several practical... |

28 |
Trace Algebra for Automatic Verification of Real-Time Concurrent Systems
- Burch
- 1992
(Show Context)
Citation Context ...if conservative timing constraints are added. The timed implementation for the MMU controller and the refresh cycle of the DRAM controller have been verified using Burch's timed circuit verifier [24] =-=[25]-=- to be hazard-free under the given timing constraints. Here, hazard-freedom is defined to mean that no transition once enabled to occur can be disabled without it occurring. 5 Conclusions and Future R... |

21 |
Synthesis and optimization of interface transducer logic
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- 1987
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Citation Context ...te acyclic graph into a finite acyclic graph so that these algorithms can be used to correctly detect redundant circuitry. Using timing constraints to simplify asynchronous circuits is not a new idea =-=[4]-=- [5]; however, most of these techniques were based on adding delay elements to avoid circuit hazards. We will show that hazard-free timed circuits can be synthesized without suffering any further dela... |

21 |
Formal program transformations for VLSI circuit synthesis
- Martin
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Citation Context ...mplementation Several methods exist which transform a state graph into a circuit implementation such as those described in [2] [3] [4]. We present a method similar to guard strengthening described in =-=[21]-=- but derive the circuit implementations from a state graph. A guard is a conjunction of signals and their negations. When this conjunction evaluates to true, the transition it is guarding can occur. T... |

20 |
Specification and analysis of timing constraints in signal transition graphs
- Vanbekbergen, Goossens, et al.
- 1992
(Show Context)
Citation Context ..., it is necessary to determine the difference in the possible firing times between two transitions in a circuit specification. Recently, polynomial time algorithms have been developed by Vanbekbergen =-=[1]-=- and Dill [2] to determine this value for acyclic graphs. To apply these algorithms to circuit synthesis, these results must be expanded to handle cyclic specifications. One approach to this problem i... |

14 |
Private Communication
- Chu
- 1998
(Show Context)
Citation Context ...g and 0 otherwise, and �� = [l; u] where l is the lower bound and u is the upper bound of the timing constraint on the rule. As an example, a SCSI protocol controller, originally specified with a =-=STG [20]-=-, is specified by its cyclic constraint graph as shown in Figure 1. An example of a rule in this constraint graph is between the two events q # and rdy #, which is of the form hq #; rdy #; 0; [0; 5]i.... |

14 |
Modeling timing assumptions with trace theory,” ICCD
- Burch
- 1989
(Show Context)
Citation Context ...bles if conservative timing constraints are added. The timed implementation for the MMU controller and the refresh cycle of the DRAM controller have been verified using Burch's timed circuit verifier =-=[24]-=- [25] to be hazard-free under the given timing constraints. Here, hazard-freedom is defined to mean that no transition once enabled to occur can be disabled without it occurring. 5 Conclusions and Fut... |

13 | Synthesis of verifiably hazard-free asynchronous control circuits
- Lavagno, Sangiovanni-Vincentelli
- 1991
(Show Context)
Citation Context ...cyclic graph into a finite acyclic graph so that these algorithms can be used to correctly detect redundant circuitry. Using timing constraints to simplify asynchronous circuits is not a new idea [4] =-=[5]-=-; however, most of these techniques were based on adding delay elements to avoid circuit hazards. We will show that hazard-free timed circuits can be synthesized without suffering any further delay co... |

6 |
Timing analysis of concurrent systems
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- 1992
(Show Context)
Citation Context ...s to circuit synthesis, these results must be expanded to handle cyclic specifications. Recently, an algorithm has been proposed that finds these time differences in cyclic graphs in exponential-time =-=[17]-=-. In this paper, we propose instead a polynomial-time heuristic algorithm which is sufficient for our purposes. Our algorithm unfolds the cyclic graph into an infinite acyclic graph and then examines ... |

5 |
Private communication
- Yun
- 1993
(Show Context)
Citation Context ... DRAM controller is compared with implementations from two burst-mode design styles [13] [7]. For our timed implementation, the timing constraints used for the refresh cycle are depicted in Figure 13 =-=[23]-=-. These timing constraints are derived assuming the environment is as depicted in Figure 10, and the controller is being used with a 68020/30 running at 16 to 20 MHz. The implementation of the refresh... |

3 |
The design of an asynchronous memory management unit
- Myers, Martin
- 1993
(Show Context)
Citation Context ...can be synthesized without suffering any further delay compared with speed-independent circuits, while using the timing constraints to reduce the circuit complexity. In one practical memory interface =-=[6]-=- which was designed for use with an asynchronous microprocessor [7], we were able to reduce the circuit complexity by 50 percent using very conservative timing constraints. This paper contains five se... |

1 |
Automatic Gate-Level Sythesis of Speed-Independent Circuits
- Beerel, Meng
- 1992
(Show Context)
Citation Context ...ur timed circuits retain the same behavior with less circuit complexity than earlier implementations. Many methodologies have been proposed for the synthesis of speed-independent circuits [1] [2] [3] =-=[4]-=-. Speed-independent circuits are very robust since they are guaranteed to work independent of the delays associated with their gates, but they can be overly conservative when timing constraints are kn... |