CACTI: An Enhanced Cache Access and Cycle Time Model (1996)
by
Steven J. E. Wilton
,
Norman P. Jouppi
| Venue: | IEEE Journal of Solid-State Circuits |
| Citations: | 190 - 6 self |
BibTeX
@ARTICLE{Wilton96cacti:an,
author = {Steven J. E. Wilton and Norman P. Jouppi},
title = {CACTI: An Enhanced Cache Access and Cycle Time Model},
journal = {IEEE Journal of Solid-State Circuits},
year = {1996},
volume = {31},
pages = {677--688}
}
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Abstract
This paper describes an analytical model for the access and cycle times of on-chip directmapped and set-associative caches. The inputs to the model are the cache size, block size, and associativity, as well as array organization and process parameters. The model gives estimates that are within 6% of Hspice results for the circuits we have chosen.
Citations
| 230 | An enhanced access and cycle time model for on-chip caches - Wilton, Jouppi - 1994 |
| 99 | An area model for on-chip memories and its applications - Mulder, Quach, et al. - 1991 |
| 94 | Tradeoffs in two-level on-chip caching - Jouppi, Wilton - 1994 |
| 58 | An analytical access time model for on-chip cache memories - Wada, Rajan, et al. - 1992 |
| 44 | Timing models for MOS circuits - Horowitz - 1984 |
| 10 | Signal delay inRC tree networks - Rubenstein, eld, et al. - 1983 |
| 3 | Transistor model for a Synthetic 0.8um CMOS process. Class notes for Stanford University EE371 - Johnson, Jouppi - 1990 |
| 3 | A 2ns cycle, 3,8ns access 512kb CMOS ECL RAM with a fully pipelined architecture - Chappell - 1991 |
| 1 | Post charge logic permits 4ns 18K CMOS RAM - Proebsting - 1987 |
