Exploiting Hysteresis in a CMOS Buffer
| Citations: | 1 - 1 self |
BibTeX
@MISC{Secareanu_exploitinghysteresis,
author = {Radu M. Secareanu and Victor Adler and Eby G. Friedman},
title = {Exploiting Hysteresis in a CMOS Buffer},
year = {}
}
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Abstract
A high drive CMOS buffer circuit characterized by a voltage transfer characteristic (VTC) with low threshold voltages and hysteresis is proposed. The proposed circuit is capable of restoring slow transition times and distorted input signals with a minimum delay penalty. Due to the hysteresis characteristic of this buffer, a comparison with a Schmitt-trigger is provided. An important application of this circuit is the restoration of slow transitioning signals propagated along an RC interconnect. The circuit can be used in conjunction with existing repeater insertion methodologies to decrease the delay of an RC line.
Citations
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| 18 | Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load. Analog Integr. Circuit Signal - Adler, Friedman - 1997 |
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| 4 | Repeater Insertion to Reduce Delay and Power in RC Tree Structures - Adler, Friedman - 1997 |
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| 2 | A High Speed CMOS Bu#er for Driving Large Capacitive Loads in Digital ASICs - Secareanu, Friedman - 1998 |
| 1 | Tuszynski, #CMOS Tapered Bu#er - Li, Haviland, et al. - 1990 |
| 1 | A Uni#ed Design Methodology for CMOS Tapered Bu#ers - Cherkauer, Friedman - 1995 |
| 1 | Design of Tapered Bu#ers with Local Interconnect Capacitance - Cherkauer, Friedman - 1995 |
