## Freescale Semiconductor

### BibTeX

@MISC{Gupta_freescalesemiconductor,

author = {Puneet Gupta and Andrew B. Kahng and Amarnath Kasibhatla and Puneet Sharma},

title = {Freescale Semiconductor},

year = {}

}

### OpenURL

### Abstract

Abstract—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard [1]. Several (suboptimal) gate sizing heuristics have been proposed over the past two decades, but research has suffered from the lack of any systematic way of assessing the quality of the proposed algorithms. We develop a method to generate benchmark circuits (called eyecharts) of arbitrary size along with a method to compute their optimal solutions using dynamic programming. We evaluate the suboptimalities of some popular gate sizing algorithms. Eyecharts help diagnose the weaknesses of existing gate sizing algorithms, enable systematic and quantitative comparison of sizing algorithms, and catalyze further gate sizing research. Our results show that common sizing methods (including commercial tools) can be suboptimal by as much as 54 % (Vt-assignment), 46 % (gate sizing) and 49 % (gate-length biasing) for realistic libraries and circuit topologies.

### Citations

2623 |
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Citation Context ...e logic gate, with PIs at the first level or stage. The delay budget assignment (without output load dependence) is essentially a multi-stage allocation problem which can be solved optimally using DP =-=[27]-=-. For an N-stage chain, the DP recursion is shown in Equations 1 and 2. We assume that a gate’s delay depends only on its size and its total output capacitance. We assume that each gate has k discrete... |

165 |
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(Show Context)
Citation Context ...nimized, subject to a maximum delay constraint. Finding the optimal gate sizing solution for a given digital logic circuit can be NP-hard [1]. Fishburn and Dunlop proposed a fast greedy method, TILOS =-=[3]-=-, to minimize area while meeting delay constraints. Chan [4] gives a pseudo-polynomial time slack-computation algorithm and a backtracking algorithm for gate sizing. Previous methods have also used ma... |

81 | D.F.: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
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Citation Context ...orithm and a backtracking algorithm for gate sizing. Previous methods have also used mathematical programming techniques to do gate sizing: linear programming (LP) [5]–[8], Lagrangian relaxation [9], =-=[10]-=-, and convex optimization [11]–[13]. Other methods include sensitivitybased approaches [2], [14]–[16], dynamic programming (DP) [17], [18] and heuristics guided by continuous programming [19]. Coudert... |

81 |
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(Show Context)
Citation Context ... input circuits. Suboptimality studies of existing heuristics have already been performed for other VLSI problems such as logic synthesis [22], placement [23], [24] and optimal buffer insertion [25], =-=[26]-=-. However, to our knowledge we are the first to investigate the suboptimalities of gate sizing heuristics in a systematic way. In this paper, we present a method to generate combinational logic circui... |

29 | New algorithms for gate sizing: a comparative study
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Citation Context ...nvex optimization [11]–[13]. Other methods include sensitivitybased approaches [2], [14]–[16], dynamic programming (DP) [17], [18] and heuristics guided by continuous programming [19]. Coudert et al. =-=[15]-=- give a good comparison of the gate sizing algorithms proposed during the early 1990s. None of the previous methods in the literature (except in [20], [21]) quantify their own suboptimality or focus o... |

29 |
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Citation Context ...gramming techniques to do gate sizing: linear programming (LP) [5]–[8], Lagrangian relaxation [9], [10], and convex optimization [11]–[13]. Other methods include sensitivitybased approaches [2], [14]–=-=[16]-=-, dynamic programming (DP) [17], [18] and heuristics guided by continuous programming [19]. Coudert et al. [15] give a good comparison of the gate sizing algorithms proposed during the early 1990s. No... |

25 | A New Class of Convex Functions for Delay Modeling and their Application to the Transistor Sizing Problem - Kasamsetty, Ketkar, et al. |

25 |
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Citation Context ...ses of input circuits. Suboptimality studies of existing heuristics have already been performed for other VLSI problems such as logic synthesis [22], placement [23], [24] and optimal buffer insertion =-=[25]-=-, [26]. However, to our knowledge we are the first to investigate the suboptimalities of gate sizing heuristics in a systematic way. In this paper, we present a method to generate combinational logic ... |

24 |
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Citation Context ...l programming techniques to do gate sizing: linear programming (LP) [5]–[8], Lagrangian relaxation [9], [10], and convex optimization [11]–[13]. Other methods include sensitivitybased approaches [2], =-=[14]-=-–[16], dynamic programming (DP) [17], [18] and heuristics guided by continuous programming [19]. Coudert et al. [15] give a good comparison of the gate sizing algorithms proposed during the early 1990... |

19 |
C.: Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
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(Show Context)
Citation Context ...n algorithm and a backtracking algorithm for gate sizing. Previous methods have also used mathematical programming techniques to do gate sizing: linear programming (LP) [5]–[8], Lagrangian relaxation =-=[9]-=-, [10], and convex optimization [11]–[13]. Other methods include sensitivitybased approaches [2], [14]–[16], dynamic programming (DP) [17], [18] and heuristics guided by continuous programming [19]. C... |

15 |
Gate-Length biasing for runtime-leakage control
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(Show Context)
Citation Context ...age, threshold voltage, gate-length and gatewidth to optimize a tradeoff of speed, area and power. The sizing problem arises at all stages of the RTL-to-GDS implementation flow, and even beyond (e.g. =-=[2]-=-). The classical problem of discrete gate sizing is to assign a size (from a pre-characterized cell library) to each gate in a combinational logic block, such that the block’s total power is minimized... |

13 |
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Citation Context ...optimal gate sizing solution for a given digital logic circuit can be NP-hard [1]. Fishburn and Dunlop proposed a fast greedy method, TILOS [3], to minimize area while meeting delay constraints. Chan =-=[4]-=- gives a pseudo-polynomial time slack-computation algorithm and a backtracking algorithm for gate sizing. Previous methods have also used mathematical programming techniques to do gate sizing: linear ... |

9 |
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Citation Context ...rithm for gate sizing. Previous methods have also used mathematical programming techniques to do gate sizing: linear programming (LP) [5]–[8], Lagrangian relaxation [9], [10], and convex optimization =-=[11]-=-–[13]. Other methods include sensitivitybased approaches [2], [14]–[16], dynamic programming (DP) [17], [18] and heuristics guided by continuous programming [19]. Coudert et al. [15] give a good compa... |

9 | Optimality and stability study of timing-driven placement algorithms
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Citation Context ...different algorithms over different classes of input circuits. Suboptimality studies of existing heuristics have already been performed for other VLSI problems such as logic synthesis [22], placement =-=[23]-=-, [24] and optimal buffer insertion [25], [26]. However, to our knowledge we are the first to investigate the suboptimalities of gate sizing heuristics in a systematic way. In this paper, we present a... |

7 | Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization,” Int'l Symposium on Quality of Electronic Design - Jeong, Kahng, et al. - 2009 |

6 | Simultaneous Vt Selection and Assignment for Leakage Optimization
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(Show Context)
Citation Context ...omial time slack-computation algorithm and a backtracking algorithm for gate sizing. Previous methods have also used mathematical programming techniques to do gate sizing: linear programming (LP) [5]–=-=[8]-=-, Lagrangian relaxation [9], [10], and convex optimization [11]–[13]. Other methods include sensitivitybased approaches [2], [14]–[16], dynamic programming (DP) [17], [18] and heuristics guided by con... |

5 | Gate Sizing For Cell Library-Based Designs
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(Show Context)
Citation Context ...sizing: linear programming (LP) [5]–[8], Lagrangian relaxation [9], [10], and convex optimization [11]–[13]. Other methods include sensitivitybased approaches [2], [14]–[16], dynamic programming (DP) =-=[17]-=-, [18] and heuristics guided by continuous programming [19]. Coudert et al. [15] give a good comparison of the gate sizing algorithms proposed during the early 1990s. None of the previous methods in t... |

4 | C.: Efficient and accurate gate sizing with piecewise convex delay models
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(Show Context)
Citation Context ... for gate sizing. Previous methods have also used mathematical programming techniques to do gate sizing: linear programming (LP) [5]–[8], Lagrangian relaxation [9], [10], and convex optimization [11]–=-=[13]-=-. Other methods include sensitivitybased approaches [2], [14]–[16], dynamic programming (DP) [17], [18] and heuristics guided by continuous programming [19]. Coudert et al. [15] give a good comparison... |

4 |
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(Show Context)
Citation Context ...: linear programming (LP) [5]–[8], Lagrangian relaxation [9], [10], and convex optimization [11]–[13]. Other methods include sensitivitybased approaches [2], [14]–[16], dynamic programming (DP) [17], =-=[18]-=- and heuristics guided by continuous programming [19]. Coudert et al. [15] give a good comparison of the gate sizing algorithms proposed during the early 1990s. None of the previous methods in the lit... |

4 | Discrete vt assignment and gate sizing using a self-snapping continuous formulation
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(Show Context)
Citation Context ...ion [9], [10], and convex optimization [11]–[13]. Other methods include sensitivitybased approaches [2], [14]–[16], dynamic programming (DP) [17], [18] and heuristics guided by continuous programming =-=[19]-=-. Coudert et al. [15] give a good comparison of the gate sizing algorithms proposed during the early 1990s. None of the previous methods in the literature (except in [20], [21]) quantify their own sub... |

4 | S.: A Network-Flow Based Cell Sizing Algorithm
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(Show Context)
Citation Context ... continuous programming [19]. Coudert et al. [15] give a good comparison of the gate sizing algorithms proposed during the early 1990s. None of the previous methods in the literature (except in [20], =-=[21]-=-) quantify their own suboptimality or focus on characterizing and investigating the suboptimalities of existing algorithms. There is no consistent benchmarking methodology when comparing sizing heuris... |

1 |
Strongly NP-Hard Discrete Gate Sizing
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(Show Context)
Citation Context ...freescale.com} Abstract—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard =-=[1]-=-. Several (suboptimal) gate sizing heuristics have been proposed over the past two decades, but research has suffered from the lack of any systematic way of assessing the quality of the proposed algor... |

1 |
PaRS: Fast and Near-optimal Grid-based Cell Sizing for Library-based Design
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(Show Context)
Citation Context ...ded by continuous programming [19]. Coudert et al. [15] give a good comparison of the gate sizing algorithms proposed during the early 1990s. None of the previous methods in the literature (except in =-=[20]-=-, [21]) quantify their own suboptimality or focus on characterizing and investigating the suboptimalities of existing algorithms. There is no consistent benchmarking methodology when comparing sizing ... |