Towards an Algebraic Synthesis of Verilog

Towards an Algebraic Synthesis of Verilog (2001)

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by Juliano Iyoda , He Jifeng

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3 - 1 self

BibTeX

@MISC{Iyoda01towardsan,
    author = {Juliano Iyoda and He Jifeng},
    title = {Towards an Algebraic Synthesis of Verilog},
    year = {2001}
}

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Abstract

This report presents an initial step towards a correct synthesis of Verilog. The synthesis is performed by reducing the source program to a normal form through the application of a small set of algebraic laws and subsequent mapping to the Xilinx Netlist Format. Our synthesis approach eliminates semantic mismatch between the Verilog model and the synthesized netlist.

Citations

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