## Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors (2001)

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Venue: | Journal of Symbolic Computation |

Citations: | 86 - 12 self |

### BibTeX

@INPROCEEDINGS{Velev01effectiveuse,

author = {Miroslav N. Velev},

title = {Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors},

booktitle = {Journal of Symbolic Computation},

year = {2001},

pages = {226--231}

}

### Years of Citing Articles

### OpenURL

### Abstract

We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We identify one SAT-checker that significantly outperforms the rest. We evaluate ways to enhance its performance by variations in the generation of the Boolean correctness formulas. We reassess optimizations previously used to speed up the formal verification and probe future challenges.

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Citation Context ...lementation of its functional units. However, that more general problem is easier to prove. Two possible ways to impose the property of functional consistency of UFs and UPs are Ackermann constraints =-=[1]-=- and nested ITEs [3][4][21]. The Ackermann scheme replaces each UF (UP) application in the EUFM formula F with a new domain variable (propositional variable) and then adds external consistency constra... |

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Citation Context ...each clock cycle, where k is the issue width of the design. The correctness formula is then translated to a Boolean formula by an automatic tool [55] that exploits the properties of Positive Equality =-=[8]-=-, the e ij encoding [18], and a number of conservative approximations. The resulting Boolean formula should be a tautology in order for the processor to be correct and can be evaluated by any SAT proc... |

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Citation Context ...t only get the search out of local minima, but also steer it in the direction towards a global minimum—a satisfying assignment; satz [30][45], satz.v213 [30][45], satz-rand.v4.6 [19] [45], eqsatz.v2=-=0 [31]-=-; GSAT.v41 [45][47], WalkSAT.v37 [45] [46]; posit [16][45]; ntab [13][45]; rel_sat.1.0 and rel_sat.2.1 [3][45]; rel_sat_rand1.0 [19][45]; ASAT and C-SAT [15]; CLS [41]; QSAT [39] and QBF [42], two SAT... |

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Citation Context ...satz.v20 [31]; GSAT.v41 [45][47], WalkSAT.v37 [45] [46]; posit [16][45]; ntab [13][45]; rel_sat.1.0 and rel_sat.2.1 [3][45]; rel_sat_rand1.0 [19][45]; ASAT and C-SAT [15]; CLS [41]; QSAT [39] and QBF =-=[42]-=-, two SAT-checkers for quantified Boolean formulas; ZRes [11], a SAT-checker combining ZeroSupressed BDDs (ZBDDs) with the original Davis-Putnam procedure; BSAT and IS-USAT, both based on BDDs and exp... |

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Citation Context ...h the original Davis-Putnam procedure; BSAT and IS-USAT, both based on BDDs and exploiting the properties of unate Boolean functions [29]; Prover, a commercial SAT-checker based on Stålmarck’s meth=-=od [50]-=-; HeerHugo [20], also based on the same method; and Chaff [38], a complete SAT-checker exploiting lazy Boolean constraint propagation, non-chronological backtracking, restarts, randomization, and many... |

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Citation Context ... k is the issue width of the design. The correctness formula is then translated to a Boolean formula by an automatic tool [55] that exploits the properties of Positive Equality [8], the e ij encoding =-=[18]-=-, and a number of conservative approximations. The resulting Boolean formula should be a tautology in order for the processor to be correct and can be evaluated by any SAT procedure. The syntax of EUF... |

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Citation Context ...fy Chaff [38] as the most efficient SAT-checker for the second verification strategy when applied to both correct and buggy designs. Chaff significantly outperforms BDDs [7] and the SAT-checker DLM-2 =-=[48]-=-, the previous most efficient SAT procedures for, respectively, correct and buggy processors. We reevaluate optimizations used to enhance the performance of BDDs and DLM-2 and conclude that many of th... |

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Citation Context ...rrors. 4 Comparison of SAT Procedures We evaluated 28 SAT-checkers: SATO.3.2.1 [44][63]; GRASP [17][32] [33], used both with a single strategy and with restarts, randomization, and recursive learning =-=[2]-=-; CGRASP [12][34], a version of GRASP that exploits structural information; DLM-2 and DLM-3 [48], as well as DLM-2000 [62], all incomplete SATcheckers (i.e., they cannot prove unsatisfiability) based ... |

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Citation Context ...to false, and that of a g-term domain variable with a syntactically distinct g-term domain variable (a g-equation) could evaluate to either true or false and can be encoded with Boolean variables [18]=-=[40].-=- 3 Microprocessor Benchmarks We base our comparison of SAT procedures on a set of high-level microprocessors, ranging from a single-issue 5-stage pipelined DLX [23], 1×DLX-C, to a dual-issue supersca... |

43 | Formal Verification of Superscalar Microprocessors with Multicycle Functional Units
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Citation Context ...icroprocessors, ranging from a single-issue 5-stage pipelined DLX [23], 1×DLX-C, to a dual-issue superscalar DLX with multicycle functional units, exceptions, and branch prediction, 2×DLX-CC-MC-EX-B=-=P [56]-=-, to a 9-wide VLIW architecture, 9VLIW-MC-BP [57], that imitates the Intel Itanium [25] [49] in speculative features such as predicated execution, speculative register remapping, advanced loads, and b... |

43 | Combining decision diagrams and SAT procedures for efficient symbolic model checking
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Citation Context ... (BDDs) [7] and Boolean Expression Diagrams (BEDs) [61]---the latter not being a canonical representation of Boolean functions, but shown to be extremely efficient when formally verifying multipliers =-=[60]-=-. The translation to the CNF format [28], used as input to most SAT-checkers, was done after inserting a negation at the top of the Boolean correctness formula that has to be a tautology in order for ... |

42 | The Impact of Branching Heuristics in Propositional Satisfiability Algorithms
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Citation Context ...7][36]. The bugs were spread over the entire designs and occurred either as single or multiple errors. 4 Comparison of SAT Procedures We evaluated 28 SAT-checkers: SATO.3.2.1 [44][63]; GRASP [17][32] =-=[33]-=-, used both with a single strategy and with restarts, randomization, and recursive learning [2]; CGRASP [12][34], a version of GRASP that exploits structural information; DLM-2 and DLM-3 [48], as well... |

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Citation Context ...Davis-Putnam procedure; BSAT and IS-USAT, both based on BDDs and exploiting the properties of unate Boolean functions [29]; Prover, a commercial SAT-checker based on Stålmarck’s method [50]; HeerHu=-=go [20]-=-, also based on the same method; and Chaff [38], a complete SAT-checker exploiting lazy Boolean constraint propagation, non-chronological backtracking, restarts, randomization, and many optimizations.... |

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Citation Context ...n In the past few years, SAT-checkers have made a dramatic improvement in both their speed and capacity. We compare 28 of them with decision diagrams—BDDs [7] and BEDs [61]—as well as with ATPG to=-=ols [21]-=-[52] when used as Boolean Satisfiability (SAT) procedures in the formal verification of microprocessors. The comparison is based on two benchmark suites, each of 101 Boolean formulas generated in the ... |

35 | Boolean satisfiability with transitivity constraints
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Citation Context ...nally, e.g., by triangulating the comparison graph of those eij variables that affect the final Boolean formula and then enforcing transitivity for each of the resulting triangles—sparse transitivit=-=y [9]-=-. Although not every correct microprocessor requires transitivity for its correctness proof, that property is needed in order to avoid false negatives for buggy processors or for designs that do need ... |

34 | SAT-encodings, search space structure, and local search performance
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Citation Context ...ith the e ij encoding. As a result, the small domains encoding is less efficient than the e ij encoding. In a different application---encoding constraint satisfaction problems as SAT instances---Hoos =-=[24]-=- similarly found that better performance is achieved with an encoding that introduces more variables but results in conceptually simpler search spaces. 7 Benefits of Conservative Approximations and Po... |

32 | Multi-resolution on compressed sets of clauses
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Citation Context ...t [16][45]; ntab [13][45]; rel_sat.1.0 and rel_sat.2.1 [3][45]; rel_sat_rand1.0 [19][45]; ASAT and C-SAT [15]; CLS [41]; QSAT [39] and QBF [42], two SAT-checkers for quantified Boolean formulas; ZRes =-=[11]-=-, a SAT-checker combining ZeroSupressed BDDs (ZBDDs) with the original Davis-Putnam procedure; BSAT and IS-USAT, both based on BDDs and exploiting the properties of unate Boolean functions [29]; Prove... |

23 |
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Citation Context ...[19] [45], eqsatz.v20 [31]; GSAT.v41 [45][47], WalkSAT.v37 [45] [46]; posit [16][45]; ntab [13][45]; rel_sat.1.0 and rel_sat.2.1 [3][45]; rel_sat_rand1.0 [19][45]; ASAT and C-SAT [15]; CLS [41]; QSAT =-=[39]-=- and QBF [42], two SAT-checkers for quantified Boolean formulas; ZRes [11], a SAT-checker combining ZeroSupressed BDDs (ZBDDs) with the original Davis-Putnam procedure; BSAT and IS-USAT, both based on... |

21 |
An Efficient
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Citation Context ...ark suites [22][26][27][36]. The bugs were spread over the entire designs and occurred either as single or multiple errors. 4 Comparison of SAT Procedures We evaluated 28 SAT-checkers: SATO.3.2.1 [44]=-=[63]-=-; GRASP [17][32] [33], used both with a single strategy and with restarts, randomization, and recursive learning [2]; CGRASP [12][34], a version of GRASP that exploits structural information; DLM-2 an... |

19 | Random Generation of Test Instances for Logic Optimizers
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- 1994
(Show Context)
Citation Context ...ve update of a user-visible state element when the speculation is incorrect. Hence, the variations introduced were not completely random, as done in other efforts to generate benchmark suites [22][26]=-=[27]-=-[36]. The bugs were spread over the entire designs and occurred either as single or multiple errors. 4 Comparison of SAT Procedures We evaluated 28 SAT-checkers: SATO.3.2.1 [44][63]; GRASP [17][32] [3... |

19 | Algebraic simplification techniques for propositional satisfiability
- Marques-Silva
- 2000
(Show Context)
Citation Context ...terexample, we terminate the rest, and consider the minimum time as the verification time. As shown, the difference between BDDs and Chaff is up to 4 orders of magnitude. Applying the script simplify =-=[35]-=- in order to perform algebraic simplifications on the CNF formula for one of the buggy VLIW designs required more than 47,000 seconds, while Chaff took only 14 seconds to find a satisfying assignment ... |

17 | Formal Verification of VLIW Microprocessors with Speculative Execution
- Velev
- 2000
(Show Context)
Citation Context ...ge pipelined DLX [23], 1×DLX-C, to a dual-issue superscalar DLX with multicycle functional units, exceptions, and branch prediction, 2×DLX-CC-MC-EX-BP [56], to a 9-wide VLIW architecture, 9VLIW-MC-B=-=P [57]-=-, that imitates the Intel Itanium [25] [49] in speculative features such as predicated execution, speculative register remapping, advanced loads, and branch prediction. The VLIW design is far more com... |

15 | Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
- Velev
- 2001
(Show Context)
Citation Context ...ormula, term1, term2) will evaluate to term1 when formula = true and to term2 when formula = false. The syntax for terms can be extended to model memories by means of the functions read and write [10]=-=[59]-=-. Formulas are used in order to model the control path of a microprocessor, as well as to express the correctness condition. A formula can be an Uninterpreted Predicate (UP) applied on a list of argum... |

12 | Design of experiments for evaluation of BDD packages using controlled circuit mutations, in
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- 1998
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Citation Context ...peculative update of a user-visible state element when the speculation is incorrect. Hence, the variations introduced were not completely random, as done in other efforts to generate benchmark suites =-=[22]-=-[26][27][36]. The bugs were spread over the entire designs and occurred either as single or multiple errors. 4 Comparison of SAT Procedures We evaluated 28 SAT-checkers: SATO.3.2.1 [44][63]; GRASP [17... |

11 |
and H.Fujiwara, “A Neutral Netlist of 10
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- 1985
(Show Context)
Citation Context ...n formulas generated in the verification of 1 correct and 100 buggy versions of the same design—a superscalar and a VLIW microprocessor, respectively. Unlike existing benchmark suites, e.g., ISCAS 8=-=5 [5]-=- and ISCAS 89 [6], which are collections of circuits that have nothing in common, our suites are based on the same correct design and hence provide a point for consistent comparison of different evalu... |

11 |
Boolean satisfiability
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- 2000
(Show Context)
Citation Context ...son of SAT Procedures We evaluated 28 SAT-checkers: SATO.3.2.1 [44][63]; GRASP [17][32] [33], used both with a single strategy and with restarts, randomization, and recursive learning [2]; CGRASP [12]=-=[34]-=-, a version of GRASP that exploits structural information; DLM-2 and DLM-3 [48], as well as DLM-2000 [62], all incomplete SATcheckers (i.e., they cannot prove unsatisfiability) based on global random ... |

10 |
Stochastic Local Search in Constrained Spaces
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Citation Context ...-rand.v4.6 [19] [45], eqsatz.v20 [31]; GSAT.v41 [45][47], WalkSAT.v37 [45] [46]; posit [16][45]; ntab [13][45]; rel_sat.1.0 and rel_sat.2.1 [3][45]; rel_sat_rand1.0 [19][45]; ASAT and C-SAT [15]; CLS =-=[41]-=-; QSAT [39] and QBF [42], two SAT-checkers for quantified Boolean formulas; ZRes [11], a SAT-checker combining ZeroSupressed BDDs (ZBDDs) with the original Davis-Putnam procedure; BSAT and IS-USAT, bo... |

8 | A BDD-Based Satisfiability Infrastructure Using the Unate Recursive
- Kalla, Zeng, et al.
- 2000
(Show Context)
Citation Context ...; ZRes [11], a SAT-checker combining ZeroSupressed BDDs (ZBDDs) with the original Davis-Putnam procedure; BSAT and IS-USAT, both based on BDDs and exploiting the properties of unate Boolean functions =-=[29]; P-=-rover, a commercial SAT-checker based on Stålmarck’s method [50]; HeerHugo [20], also based on the same method; and Chaff [38], a complete SAT-checker exploiting lazy Boolean constraint propagation... |

8 | Formal Verification Based on Boolean Expression Diagrams,” 3
- Williams
- 2000
(Show Context)
Citation Context ...future challenges. 1 Introduction In the past few years, SAT-checkers have made a dramatic improvement in both their speed and capacity. We compare 28 of them with decision diagrams—BDDs [7] and BED=-=s [61]��-=-�as well as with ATPG tools [21][52] when used as Boolean Satisfiability (SAT) procedures in the formal verification of microprocessors. The comparison is based on two benchmark suites, each of 101 Bo... |

8 | Solving Hard Satisfiability Problems: A Unified Algorithm Based on Discrete Lagrange Multipliers
- Wu, Wah
- 1999
(Show Context)
Citation Context ...ith a single strategy and with restarts, randomization, and recursive learning [2]; CGRASP [12][34], a version of GRASP that exploits structural information; DLM-2 and DLM-3 [48], as well as DLM-2000 =-=[62]-=-, all incomplete SATcheckers (i.e., they cannot prove unsatisfiability) based on global random search and discrete Lagrangian Multipliers as a mechanism to not only get the search out of local minima,... |

5 |
Collection and analysis of microprocessor design errors
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- 2000
(Show Context)
Citation Context ...ions of both 2×DLX-CC-MCEX-BP and 9VLIW-MC-BP. The bugs were variants of actual errors made in the design of the correct versions and also coincided with the types of bugs that Van Campenhout, et al.=-= [54]-=- analyzed to be among the most frequent design errors. The injected bugs included omitting inputs to logic gates, e.g., an instruction is not squashed when a preceding branch is taken or a stalling co... |

5 | Collection and Analysis of Microprocessor Design Errors
- Campenhout, Mudge, et al.
- 2000
(Show Context)
Citation Context ...ions of both 2×DLX-CC-MCEX-BP and 9VLIW-MC-BP. The bugs were variants of actual errors made in the design of the correct versions and also coincided with the types of bugs that Van Campenhout, et al. =-=[54]-=- analyzed to be among the most frequent design errors. The injected bugs included omitting inputs to logic gates, e.g., an instruction is not squashed when a preceding branch is taken or a stalling co... |

4 |
Validity Checker (SVC
- Stanford
(Show Context)
Citation Context ...aluation methods. The correctness condition that we use is expressed in a decidable subset of First-Order Logic [10]. That allows it either to be checked directly with a customized decision procedure =-=[51]-=- or to be translated to an equivalent Boolean formula [55] that can be evaluated with SAT engines for either proving correctness or finding a counterexample. The latter approach can directly benefit f... |