## Piecewise Linear Models for Switch-Level Simulation (1992)

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Citations: | 4 - 2 self |

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@MISC{Kao92piecewiselinear,

author = {Russell Kao},

title = {Piecewise Linear Models for Switch-Level Simulation},

year = {1992}

}

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### Abstract

### Citations

767 |
Data Structures and Algorithms
- Aho, Hopcroft, et al.
- 1983
(Show Context)
Citation Context ...om the graphs of ECL gates was the primary motivation behind neglecting the output conductance of bipolar transistors. 8 A topological sort can be performed by depth first search with complexity O(n) =-=[AHU85]-=-. CHAPTER 5. MOMENT COMPUTATION 80 cluster 1 2 1 4 6 5 3 Figure 60: Resistor Model for Bipolar Transistor Results in Loops in ECL Gates 5.6 Relaxing Network Restrictions In the preceding section a met... |

439 |
Rohrer: Asymptotic waveform evaluation for timing analysis
- Pillage, A
- 1990
(Show Context)
Citation Context ...wise linear model, we investigate the incorporation of more general piecewise linear transistor models into the switch-level framework. 2 Several considerations motivate the use of piecewise 2 Pillage=-=[Pil89]-=- suggested the incorporation of piecewise linear models and moment analysis into a circuit simulator as a promising future application of his work. Our work differs in emphasis. We neglect the general... |

396 |
The transient response of damped linear networks
- Elmore
- 1948
(Show Context)
Citation Context ...on that the response is computed once for all time rather than at numerous points in time. CHAPTER 2. PREVIOUS WORK IN TRANSIENT ESTIMATION 14 Moment analysis originated in the late 1940's when Elmore=-=[Elm48]-=- utilized the first and second moments of the impulse response of a linear amplifier to estimate its step response. In general, the kth moment of the (presumed causal) impulse response, h(t), is defin... |

345 |
An Introduction to Numerical Analysis
- Atkinson
- 1989
(Show Context)
Citation Context ...his chapter. 6.2 Overview of Root Finding Although many general purpose root finding techniques have been described in the literature (for example, Bisection, Newton Raphson, regula falsi, and Brent's=-=[Atk78]-=-), there exists no general technique which 1) offers any control over which root is found, 2) provides any guarantee of convergence or 3) can detect when no root exists. Instead, in order to guarantee... |

277 |
SPICE2: A Computer Program to Simulate Semiconductor Circuits", Memorandum No
- Nagel
- 1975
(Show Context)
Citation Context ...he previous time step or Newton Raphson iteration was simply reused. Thus, the needless reevaluation of subcircuits that were not changing was bypassed much in the same way that SPICE bypassed devices=-=[Nag75]. Relaxati-=-on MOTIS[CGK75] was the first of the so called "timing simulators" that utilized restricted circuit models, nonlinear relaxation, and time advancement integration. When certain restrictions ... |

196 | Signal Delay in RC Tree Networks
- Rubinstein, Penfield, et al.
- 1983
(Show Context)
Citation Context ... The delay estimate became known as the Elmore delay. Interest in the application of moment analysis to the modeling of delays in MOS digital integrated circuits was sparked by Penfield and Rubinstein=-=[PR81]-=- who modeled the delay of polysilicon interconnect by the step response of RC trees. An RC tree was defined to be a tree of resistors with one grounded node and grounded capacitors at the other nodes ... |

82 | The Design and Analysis of VLSI Circuits - Glasser, Dobberpuhl - 1985 |

79 |
Device Electronics for Integrated Circuits
- Muller, Kamins
- 1986
(Show Context)
Citation Context ...s proportional to the number of hyperplanes bounding the current region. 5 The variation of drain current with the drain--source voltage in the saturation region is caused by channel length modulation=-=[MK77]-=- 6 The dependence of the model's threshold upon the drain voltage is explained in Appendix A. CHAPTER 3. PIECEWISE LINEAR MODELS 31 3.4.3 Choosing Parameters In exchange for its simplicity, the Level-... |

58 |
IRSIM: An Incremental MOS Switch-Level Simulator
- Salz, Horowitz
- 1989
(Show Context)
Citation Context ... approach loses its speed advantage for those cases where the full accuracy and flexibility of circuit simulation are desired. 1 SPICE--3d2 is a derivative of the circuit simulator SPICE[Nag75], Irsim=-=[SH89]-=- is a derivative of the MOS switch level simulator Rsim[Ter83], and Bisim is an ECL switch-level simulator[KAHS88]. Although Irsim is an incremental simulator, its incremental capabilities aren't used... |

54 |
Timing Models for MOS Circuits
- Horowitz
- 1983
(Show Context)
Citation Context ...initially intended to model the delays of linear interconnect, it was soon used by a number of MOS timing analyzers[Put82, Jou83] to model the delays of networks of nonlinear MOS transistors. Horowitz=-=[Hor83]-=- more carefully justified this approach by deriving nonlinear one and two time constant waveform estimates and bounds. He then retrofitted his nonlinear timing models into an existing switch-level sim... |

53 |
The numerical treatment of a single nonlinear equation
- Householder
- 1970
(Show Context)
Citation Context .... Instead, theorems that predict the number of roots that lie along segments of the real axis allow us to narrow in on the single real root of interest. In particular we employ Decartes' rule of signs=-=[Hou70]-=-: Definition 1 Given a sequence of real numbers a 0 ; a 1 ; : : : a n a variation in sign occurs if a i a i+1 ! 0 or if a i a i+j ! 0 and a i+1 = a i+2 = : : : = a i+j \Gamma1 = 0. Theorem 1 (Decartes... |

49 | Semiconductor Device Modeling with Spice - Antognetti - 1988 |

32 | Computing signal delay in general RC networks by tree/link partitioning,” in
- Chan, Karplus
- 1990
(Show Context)
Citation Context ... procedures do not have linear complexity, if the number of loops is small, they can be nearly as efficient. Lin and Mead[LM84] proposed an algorithm based on Gauss-Seidel relaxation. Chan and Karplus=-=[CK89]-=- and Pillage and Dutta[PD90] handle edges closing loops in the tree using branch tearing. Ratzlaff et al.[RGP91] utilize a procedure that can be viewed as the application of node tearing techniques. 1... |

32 |
Signal Delay in General RC Networks
- Lin, Mead
- 1984
(Show Context)
Citation Context ...sis have been proposed to handle circuits that are nearly trees. Although these procedures do not have linear complexity, if the number of loops is small, they can be nearly as efficient. Lin and Mead=-=[LM84]-=- proposed an algorithm based on Gauss-Seidel relaxation. Chan and Karplus[CK89] and Pillage and Dutta[PD90] handle edges closing loops in the tree using branch tearing. Ratzlaff et al.[RGP91] utilize ... |

27 |
MOTIS - an MOS timing simulator
- Chawla, Gummel, et al.
- 1975
(Show Context)
Citation Context ...Newton Raphson iteration was simply reused. Thus, the needless reevaluation of subcircuits that were not changing was bypassed much in the same way that SPICE bypassed devices[Nag75]. Relaxation MOTIS=-=[CGK75] was the f-=-irst of the so called "timing simulators" that utilized restricted circuit models, nonlinear relaxation, and time advancement integration. When certain restrictions were placed on the circui... |

27 |
P.M.Lin, 'Computer Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
- Chua
- 1975
(Show Context)
Citation Context ...e CHAPTER 5. MOMENT COMPUTATION 74 (b) 2 v v e -t/p2-t/p1 1 e 5 (a) Figure 52: Transistor-capacitor tree. v 2 i 2 1 v 1 Figure 53: Three terminal network model. ports, one from each terminal to ground=-=[CL75]-=-. 5 2 4 i 1 i 2 3 5 = 2 4 y 11 y 12 y 21 y 22 3 5 2 4 v 1 v 2 3 5 + 2 4 i s1 i s2 3 5 (57) Figure 54 gives a physical interpretation of the six parameters of the admittance formulation. y 2 v 12 1 s1 ... |

25 | Analysis and Design of Digital Integrated Circuits - Hodges, Jackson, et al. - 2003 |

24 | RICE: Rapid Interconnect Circuit Evaluation Using AWE - Ratzlaff, Pillage - 1994 |

23 |
Simulation tools for digital LSI design
- Terman
- 1983
(Show Context)
Citation Context ...n existing switch-level simulator 4 , 4 Although, this work has not been widely reported in the literature, it was performed as part of his PhD CHAPTER 2. PREVIOUS WORK IN TRANSIENT ESTIMATION 15 Rsim=-=[Ter83]-=-. Because this thesis is essentially an extension of Rsim we next describe in greater detail the algorithms used by Rsim. As mentioned in the introduction, Rsim models transistors with the simple resi... |

21 |
Improved Models for Switch-Level Simulation
- Chu
- 1988
(Show Context)
Citation Context ...es[Wya85, LM84], and floating capacitors and controlled sources[SZ87]. Also explored was the use of higher order estimates to model the non-monotonic waveforms arising from linear[RT85a] and nonlinear=-=[Chu88]-=- charge sharing. However, many of the extensions to linear moment analysis were superceded by the recent discovery[Hua90, Cha91] that single time constant delay estimation was just a special case of t... |

17 | Modeling and simulation of VLSI interconnections with moments - McCormick - 1989 |

14 |
M.Horowitz, "Techniques for calculating currents and voltages in VLSI power supply networks
- Stark
- 1990
(Show Context)
Citation Context ...a combination of tearing techniques. Branch tearing is used to reduce individual 10 This was an improvement of a technique first explored by Stark and Horowitz for the solution of large power networks=-=[SH90]-=-. CHAPTER 5. MOMENT COMPUTATION 86 clusters to leaky trees. 11 The difference between our approach and that of Chan and Karplus[CK89] and Pillage and Dutta[PD90] is that we needn't tear branches to gr... |

14 |
Solution of large-scale networks by tearing
- Wu
- 1976
(Show Context)
Citation Context ...dependently and 3) combining the independent solutions to produce the overall solution. Two particularly interesting techniques have been devised for tearing systems of nodal equations: branch tearing=-=[Wu76] and node -=-tearing[SVCC77]. Branch tearing can be interpreted as 9 the insertion of independent current sources in series with "torn" branches in order to partition the network (Figure 63). In contrast... |

12 |
Sparse matrix techniques
- Kundert
- 1986
(Show Context)
Citation Context ...the Jacobian of an entire IC can be prohibitively expensive. Even using sparse techniques, the inversion of circuit matrices has been empirically observed to grow superlinearly (for example, O(n 1:5 )=-=[Kun86]-=-) with the circuit size. Furthermore, because a single time step is chosen for the entire circuit, the step size is necessarily limited by the accuracy requirements of the fastest moving subcircuit. T... |

11 |
Padé approximation of linear(ized) circuit responses
- Huang
- 1990
(Show Context)
Citation Context ...stimate generated by RC tree analysis[PR90]. Furthermore, as j approaches the order of the actual system being approximated, the Pade approximation,sH(s), converges to the actual system function, H(s)=-=[Hua90]-=-. 4.3 Practical Considerations Although in principle moments matching encompasses approximations of arbitrary order, in practice it may be impossible to produce an approximation if the order is too hi... |

11 |
Techniques for the simulation of large-scale integrated circuits
- Newton
- 1979
(Show Context)
Citation Context ...ion and Newton-Raphson iteration. MOTIS was followed by a number of simulators that explored variations of the relaxation procedure. Event-driven techniques from logic simulation were used by SPLICE1 =-=[New79]-=- to 1) dynamically order the equations thereby achieving faster convergence and 2) bypass the evaluation of latent nodes. Problems with reliability motivated the investigation of alternatives to Gauss... |

10 |
Tensor Analysis of Networks
- Kron
- 1939
(Show Context)
Citation Context ...this section we will show that the circuit decomposition technique known as tearing can be used to handle such circuits. 5.6.1 Node and Branch Tearing Circuit tearing was originally introduced by Kron=-=[Kro39]-=- who described the solution of large networks by 1) partitioning them into multiple subnetworks 2) solving the subnetworks independently and 3) combining the independent solutions to produce the overa... |

10 |
A multilevel Newton algorithm with macromodeling and latency for the analysis of large-scale nonlinear circuits in the time domain
- Rabbat, Sangiovanni-Vincentelli, et al.
- 1979
(Show Context)
Citation Context ...'t actively switching. We will describe three common techniques that were used to decompose the circuit equations (4): circuit tearing, relaxation, and forward Euler integration. Circuit Tearing Macro=-=[RSVH79]-=- and Slate[YHT80] employed circuit tearing techniques to reduce the Jacobian to bordered block diagonal form. Once in this form the system of equations could be solved in two steps. First, each of the... |

8 |
A survey of third-generation simulation techniques
- Hachtel, Sangiovanni-Vincentelli
- 1981
(Show Context)
Citation Context ...of computer memory and time. Consequently, a "third generation" of simulators emerged which attempted to accelerate the transient simulation of large digital ICs. 1 Hachtel and Sangiovanni-V=-=incentelli[HSV81]-=- have found it to be convenient to distinguishbetween three generations of simulators. 7 CHAPTER 2. PREVIOUS WORK IN TRANSIENT ESTIMATION 8 2.1.1 Circuit Simulation Circuit simulators represent the IC... |

8 |
Circuit Partitioning Simplified
- Rohrer
- 1988
(Show Context)
Citation Context ... partitions the network into three subnetworks. The network is considered to be 9 The intuition behind these interpretations of branch and node tearing are largely due to an insightful paper by Rohrer=-=[Roh88]. However,-=- our interpretation of node tearing differs from the one presented there. CHAPTER 5. MOMENT COMPUTATION 83 2 2 i v i 1 v 1 Figure 64: Circuit Partitioning via Node Tearing. "partitioned" bec... |

8 | Iterated timing analysis and SPLICE1
- Saleh, Kleckner, et al.
- 1983
(Show Context)
Citation Context ...DMNSV83] algorithms. Additionally, it was realized that relaxation could be applied at different levels, including at the linear equation level (MOTIS2[CS84]), the nonlinear equation level (SPLICE 1.6=-=[Sal83]-=-) and the waveform level (Relax[LSV82]). Forward Euler Integration A different approach to decoupling Equation (4) was explored by Elogic[KKSN84] and SPECS[dG84]. When certain restrictions were placed... |

7 |
An algorithm for MOS logic simulation
- Bryant
- 1980
(Show Context)
Citation Context ...he circuit is described as a network of transistors that are simply modeled by voltage controlled switches. Depending upon the particular approach, each switch has associated with it either a strength=-=[Bry80]-=- or a resistance[Ter83, RT85b] representing the current driving capabilities of the transistor (Figure 4). Because the circuit isn't partitioned into unidirectional gates, switch level simulators elim... |

7 | TV: an nMOS Timing Analyzer - Jouppi - 1983 |

7 | Signal delay in RC mesh networks - Wyatt - 1985 |

7 | Algorithms for ASTAP-A network analysis program - Weeks, Jiminez, et al. - 1973 |

6 |
The second generation MOTIS timing simulator - An efficient and accurate approach for general MOS circuit
- Chen, Subramanyam
- 1984
(Show Context)
Citation Context ...idel[New79], and Modified Symmetric Gauss-Seidel[DMNSV83] algorithms. Additionally, it was realized that relaxation could be applied at different levels, including at the linear equation level (MOTIS2=-=[CS84]-=-), the nonlinear equation level (SPLICE 1.6[Sal83]) and the waveform level (Relax[LSV82]). Forward Euler Integration A different approach to decoupling Equation (4) was explored by Elogic[KKSN84] and ... |

6 |
Rapid interconnect circuit evaluator
- RICE
- 1999
(Show Context)
Citation Context ...n and Mead[LM84] proposed an algorithm based on Gauss-Seidel relaxation. Chan and Karplus[CK89] and Pillage and Dutta[PD90] handle edges closing loops in the tree using branch tearing. Ratzlaff et al.=-=[RGP91]-=- utilize a procedure that can be viewed as the application of node tearing techniques. 1 General purpose circuit analysis techniques have also been applied to moment computation. Shi and Zhang[SZ87] f... |

5 |
A Survey of Simple Transfer-Function Derivations from High-Order State-Variable Models
- Bosley, Lees
- 1972
(Show Context)
Citation Context ...nse of the original system. The model order reduction problem has been studied extensively by linear control theorists. Of the many methods proposed, one of the simplest is based upon moments matching=-=[BL72]-=-. Although more advanced techniques demonstrating superior convergence and stability properties were subsequently derived[Cha91], none of these appears to be efficient enough for use in our particular... |

5 |
Bisim: A simulator for custom ECL circuits
- Kao, Alverson, et al.
- 1988
(Show Context)
Citation Context ... RAM sense amplifiers). Second, we would like to be able to simulate bipolar transistors which are strongly nonlinear but which seem to be adequately described by fairly simple piecewise linear models=-=[KAHS88]-=-. Meanwhile, we would like to give up as little efficiency as possible. Switch-level simulation has proven itself useful for simulating the large majority of MOS digital circuits and it would be best ... |

5 | Electricallogic simulation
- Kim, Kleckner, et al.
- 1984
(Show Context)
Citation Context ...(MOTIS2[CS84]), the nonlinear equation level (SPLICE 1.6[Sal83]) and the waveform level (Relax[LSV82]). Forward Euler Integration A different approach to decoupling Equation (4) was explored by Elogic=-=[KKSN84]-=- and SPECS[dG84]. When certain restrictions were placed on the network (including no inductors, no floating capacitors, and a grounded capacitance at each node) Nodal Analysis yields CHAPTER 2. PREVIO... |

5 |
ADAPTS: A digital transient simulation strategy for integrated circuits
- Stein, Nguyen, et al.
- 1991
(Show Context)
Citation Context ...d the simulation in terms of piecewise linear voltages and piecewise constant current device models[RV87]. Furthermore, extensions were made to include floating capacitors and inductors[VFR90]. ADAPTS=-=[SNGR91]-=- further generalized the approach by dynamically selecting each device's voltage ranges (and, hence, the step size) based upon an analytical model for the device and the accuracy requirements of the o... |

5 |
Comments on “asymptotic waveform evaluation for timing analysis
- Chan
- 1991
(Show Context)
Citation Context ...many methods proposed, one of the simplest is based upon moments matching[BL72]. Although more advanced techniques demonstrating superior convergence and stability properties were subsequently derived=-=[Cha91]-=-, none of these appears to be efficient enough for use in our particular application. The moments matching waveform approximation procedure involves two steps[PR90]. First the asymptotic final voltage... |

4 |
RELAX: A New Circuit Simulator for Large Scale Mos Integrated Circuits
- Lelarasmee, Sangiovanni-Vincentelli
- 1982
(Show Context)
Citation Context ...was realized that relaxation could be applied at different levels, including at the linear equation level (MOTIS2[CS84]), the nonlinear equation level (SPLICE 1.6[Sal83]) and the waveform level (Relax=-=[LSV82]-=-). Forward Euler Integration A different approach to decoupling Equation (4) was explored by Elogic[KKSN84] and SPECS[dG84]. When certain restrictions were placed on the network (including no inductor... |

3 |
Introductory Network Theory
- Bose, Stevens
- 1965
(Show Context)
Citation Context ... group each transistor with the voltage source driving its gate and represent the interface that the pair presents to the network by the short-circuit admittance parameters of a three terminal network=-=[BS65]-=- (Figure 53). The parameters are defined by extracting two voltage CHAPTER 5. MOMENT COMPUTATION 74 (b) 2 v v e -t/p2-t/p1 1 e 5 (a) Figure 52: Transistor-capacitor tree. v 2 i 2 1 v 1 Figure 53: Thre... |

3 |
Comments on "Asymptotic waveform evaluation for timing analysis
- Chan
- 1991
(Show Context)
Citation Context ...many methods proposed, one of the simplest is based upon moments matching[BL72]. Although more advanced techniques demonstrating superior convergence and stability properties were subsequently derived=-=[Cha91]-=-, none of these appears to be efficient enough for use in our particular application. The moments matching waveform approximation procedure involves two steps[PR90]. First the asymptotic final voltage... |

3 |
Signal Delay in RC Trees with Charge Sharing or Leakage
- Ragunathan, Thompson
- 1985
(Show Context)
Citation Context ...hu88, RT85a], RC meshes[Wya85, LM84], and floating capacitors and controlled sources[SZ87]. Also explored was the use of higher order estimates to model the non-monotonic waveforms arising from linear=-=[RT85a]-=- and nonlinear[Chu88] charge sharing. However, many of the extensions to linear moment analysis were superceded by the recent discovery[Hua90, Cha91] that single time constant delay estimation was jus... |

3 | Switch-Level Timing Simulation of MOS VLSI Circuits - Rao, Overhauser, et al. - 1989 |

3 |
Storage array and sense/refresh circuit for single-transistor memory cells
- Stein, Sihling, et al.
- 1972
(Show Context)
Citation Context ...54 140 BiNMOS Buffer 5.1 .008 650 BiCMOS RAM Cell, Read 2.3 .008 250 BiCMOS RAM Cell, Write 4.6 .012 390 Table 9: Execution Time of Example Circuits (seconds). The dynamic RAM cell and sense amplifier=-=[SSD72]-=- in Figure 74 is, perhaps, a more dramatic demonstration of the capabilities of Mom. Although Irsim can be coerced to yield a logically correct simulation of the SRAM sense amplifier if the resistance... |

3 |
A robust approach to timing verification
- Shi, Zhang
- 1987
(Show Context)
Citation Context ...tension of linear moment analysis to circuits more general than RC trees, including RC trees with multiple sources[Chu88, RT85a], RC meshes[Wya85, LM84], and floating capacitors and controlled sources=-=[SZ87]-=-. Also explored was the use of higher order estimates to model the non-monotonic waveforms arising from linear[RT85a] and nonlinear[Chu88] charge sharing. However, many of the extensions to linear mom... |

2 |
Signal delay in RC networks with floating capacitors
- Chan
- 1988
(Show Context)
Citation Context ... Raghunathan and Thompson[RT85a] and Chu and Horowitz[Chu88] extended tree analysis to handle leaky trees, multiple drivers, and charge sharing while retaining the efficiency of RC tree analysis. Chan=-=[Cha88]-=- extended RC tree analysis to handle floating capacitors. A number of derivatives of tree analysis have been proposed to handle circuits that are nearly trees. Although these procedures do not have li... |