BibTeX
@MISC{Wong_thedelft,
author = {Stephan Wong and Fakhar Anjam},
title = {The Delft Reconfigurable VLIW Processor},
year = {}
}
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Abstract
Abstract—In this paper, we present the rationale and design of the Delft reconfigurable and parameterized VLIW processor called ρ-VEX. Its architecture is based on the Lx/ST200 ISA developed by HP and STMicroelectronics. We implemented the processor on an FPGA as an open-source softcore and made it freely available. Using the ρ-VEX, we intend to bridge the gap between general-purpose and application-specific processing through parameterization of many architectural and organizational features of the processor. The parameters include: instruction set (number and type of supported instructions), the number and type of functional units (FUs), issue-width (number of slots), register file size, memory bandwidth. The parameters can be set in a static or dynamic manner in order to provide the best performance or the best utilization of available resources on the FPGA. A complete toolchain including a C compiler and a simulator is freely available. Any application written in C can be mapped to the ρ-VEX processor. This VLIW processor is able to exploit the instruction level parallelism (ILP) inherent in an application and make its execution faster compared to a RISC processor system. This project creates research opportunities in the domain of softcore embedded VLIW processor prototyping, as well as designs that can be used in high-performance applications.
Keyphrases
delft reconfigurable vliw processor file size memory bandwidth application-specific processing functional unit parameterized vliw processor vliw processor research opportunity risc processor system organizational feature instruction set vex processor high-performance application lx st200 isa complete toolchain vliw processor prototyping dynamic manner available resource open-source softcore instruction level parallelism supported instruction
