## Scalable and scalably-verifiable sequential synthesis

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Venue: | Proc. ICCAD'08. http://www.eecs.berkeley.edu/~alanmi/publications/2008/iccad08_se q.pdf A. Mishchenko |

Citations: | 18 - 14 self |

### BibTeX

@INPROCEEDINGS{Mishchenko_scalableand,

author = {Alan Mishchenko and Robert Brayton and Stephen Jang},

title = {Scalable and scalably-verifiable sequential synthesis},

booktitle = {Proc. ICCAD'08. http://www.eecs.berkeley.edu/~alanmi/publications/2008/iccad08_se q.pdf A. Mishchenko},

year = {},

pages = {27--34}

}

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### Abstract

This paper describes an efficient implementation of sequential synthesis that uses induction to detect and merge sequentiallyequivalent nodes. State-encoding, scan chains, and test vectors are essentially preserved. Moreover, the sequential synthesis results are sequentially verifiable using an independent inductive prover similar to that used for synthesis, with guaranteed completeness. Experiments with this sequential synthesis show effectiveness. When applied to a set of 20 industrial benchmarks ranging up to 26K registers and up to 53K 6-LUTs, average reductions in register and area are 12.9 % and 13.1 % respectively while delay is reduced by 1.4%. When applied to the largest academic benchmarks, an average reduction in both registers and area is more than 30%. The associated sequential verification is also scalable and runs about 2x slower than synthesis. The implementation is available in the synthesis and verification system ABC. 1

### Citations

708 | Symbolic Model Checking without BDDs
- Biere, Cimatti, et al.
- 1999
(Show Context)
Citation Context ...which may result in disproving other candidate equivalences. SAT sweeping is used as a robust combinational equivalence checking technique and as a building block in VSS. Bounded model checking (BMC) =-=[4]-=- uses Boolean satisfiability to prove a property true for all states reachable from the initial state in a fixed number of transitions (BMC depth). In the context of equivalence checking, BMC checks p... |

465 |
An Extensible SAT-solver
- Eén, Sörensson
(Show Context)
Citation Context ...ctive. 5 Experimental results The synthesis and verification algorithms are implemented in ABC [3] as commands scl, lcorr, ssw and dsec. The SAT solver used is a modified version of MiniSat-C_v1.14.1 =-=[8]-=-. The experiments targeting FPGA mapping into 6-input LUTs were run on an Intel Xeon 2-CPU 4-core computer with 8Gb of RAM. The resulting networks are verified by ISEC. The academic benchmarks used fo... |

275 | FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs - Cong, Ding - 1994 |

195 | Interpolation and SAT-Based Model Checking
- McMillan
- 2003
(Show Context)
Citation Context ...ion methodology. Future work in this area will include: • Tuning the inductive prover for scalability (for example, using unique-state constraints). • Developing new sequential engines (interpolation =-=[16]-=-, synthesizing equivalence for induction, etc). • Extending the proposed form of sequential synthesis to include (a) on-the-fly retiming [1], (b) logic restructuring using unreachable states as extern... |

122 |
Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
- Berkeley
- 2005
(Show Context)
Citation Context ...ter locations. This tends to speed up verification and help solve difficult instances by making them inductive. 5 Experimental results The synthesis and verification algorithms are implemented in ABC =-=[3]-=- as commands scl, lcorr, ssw and dsec. The SAT solver used is a modified version of MiniSat-C_v1.14.1 [8]. The experiments targeting FPGA mapping into 6-input LUTs were run on an Intel Xeon 2-CPU 4-co... |

82 |
et al. “SIS: A system for sequential circuit synthesis
- Sentovich
- 1992
(Show Context)
Citation Context ...ning now because design teams that traditionally used only CS are turning to sequential synthesis for additional delay minimization and power reduction. Scalable 1 sequential synthesis as used in SIS =-=[23]-=- is predominantly structural. It performs register sweep, which merges stuck-at-constant registers, and register retiming, which moves registers over combinational nodes while preserving the sequentia... |

76 | DAG-aware AIG rewriting a fresh look at combinational logic synthesis
- Mishchenko, Chatterjee, et al.
(Show Context)
Citation Context ... run using several IBM benchmarks. The following ABC commands were included in the scripts used to collect the experimental results: • resyn is a CS script that performs 5 iterations of AIG rewriting =-=[20]-=-. • resyn2 is a CS script that performs 10 iterations of AIG rewriting that are more diverse than those of resyn. • choice is a CS script that allows for accumulation of structural choices [6]; choice... |

67 | SAT–Based Verification without State Space Traversal
- Bjesse, Claessen
- 1954
(Show Context)
Citation Context ...anging the sequential behavior of the circuit, leading to a substantial reduction of the circuit, e.g. some pieces of logic can be discarded because they no longer affect the POs. k-step induction [9]=-=[4]-=-[21][15] can be used to efficiently compute pairs of sequentially-equivalent nodes. We call this kind of synthesis, verifiable sequential synthesis (VSS) and show that it mitigates most of the drawbac... |

44 | Improvements to combinational equivalence checking
- Mishchenko, Chatterjee, et al.
- 2006
(Show Context)
Citation Context ... the representative is a node of the class that appears first in given topological order. SAT sweeping is a technique for detecting and merging equivalent nodes in a combinational network [14][13][17]=-=[18]-=-. SAT sweeping is based on a combination of simulation and Boolean satisfiability. Random simulation is used to divide the nodes into candidate equivalence classes. Next, each pair of nodes in each cl... |

37 | FRAIGs: A unifying representation for logic synthesis and verification
- Mishchenko, Chatterjee, et al.
(Show Context)
Citation Context ...ork, the representative is a node of the class that appears first in given topological order. SAT sweeping is a technique for detecting and merging equivalent nodes in a combinational network [14][13]=-=[17]-=-[18]. SAT sweeping is based on a combination of simulation and Boolean satisfiability. Random simulation is used to divide the nodes into candidate equivalence classes. Next, each pair of nodes in eac... |

32 | Dynamic transition relation simplification for bounded property checking
- Kuehlmann
(Show Context)
Citation Context ...is work, the representative is a node of the class that appears first in given topological order. SAT sweeping is a technique for detecting and merging equivalent nodes in a combinational network [14]=-=[13]-=-[17][18]. SAT sweeping is based on a combination of simulation and Boolean satisfiability. Random simulation is used to divide the nodes into candidate equivalence classes. Next, each pair of nodes in... |

32 | A new retiming-based technology mapping algorithm for LUT-based FPGAs - Pan, Lin |

31 |
Eijk. Sequential equivalence checking based on structural similarities
- Van
(Show Context)
Citation Context ... changing the sequential behavior of the circuit, leading to a substantial reduction of the circuit, e.g. some pieces of logic can be discarded because they no longer affect the POs. k-step induction =-=[9]-=-[4][21][15] can be used to efficiently compute pairs of sequentially-equivalent nodes. We call this kind of synthesis, verifiable sequential synthesis (VSS) and show that it mitigates most of the draw... |

27 |
Exploiting suspected redundancy without proving it
- Mony, Baumgartner, et al.
(Show Context)
Citation Context ...ing the sequential behavior of the circuit, leading to a substantial reduction of the circuit, e.g. some pieces of logic can be discarded because they no longer affect the POs. k-step induction [9][4]=-=[21]-=-[15] can be used to efficiently compute pairs of sequentially-equivalent nodes. We call this kind of synthesis, verifiable sequential synthesis (VSS) and show that it mitigates most of the drawbacks l... |

26 | Scalable sequential equivalence checking across arbitrary design transformations - Baumgartner, Mony, et al. - 2007 |

25 |
Combinational and sequential mapping with priority cuts
- Mishchenko, Cho, et al.
(Show Context)
Citation Context ...ice runs resyn followed by resyn2 and collects three snapshots of the network: the original, the final, and the intermediate one saved after resyn. • if is a structural FPGA mapper with priority cuts =-=[19]-=-, finetuned area recovery, and the capacity to map over a subject graph with structural choices [6] (the mapper computes and stores at most 8 6-input priority cuts at each node; it performs five itera... |

24 | Min-area retiming on flexible circuit structures
- Baumgartner, Kuehlmann
- 2001
(Show Context)
Citation Context ...aints). • Developing new sequential engines (interpolation [16], synthesizing equivalence for induction, etc). • Extending the proposed form of sequential synthesis to include (a) on-the-fly retiming =-=[1]-=-, (b) logic restructuring using unreachable states as external don’t-cares, (c) iterative processing similar to that of combinational synthesis [20]. We also plan to make our implementation of VSS app... |

24 |
A Signal Correlation Guided ATPG Solver and its Application for Solving Difficult Industrial Cases
- Lu, Wang, et al.
- 2003
(Show Context)
Citation Context ...n this work, the representative is a node of the class that appears first in given topological order. SAT sweeping is a technique for detecting and merging equivalent nodes in a combinational network =-=[14]-=-[13][17][18]. SAT sweeping is based on a combination of simulation and Boolean satisfiability. Random simulation is used to divide the nodes into candidate equivalence classes. Next, each pair of node... |

17 | Automatic generalized phase abstraction for formal verification
- Bjesse, Kukula
- 2005
(Show Context)
Citation Context ...PI and a MUX controlled by a special register that produces 0 in the first frame and 1 afterwards. Detection of stuck-at-constant registers using ternary simulation is based on the algorithm given in =-=[5]-=-. This assigns the initial values to the registers and simulates the circuit using x-valued primary inputs. The ternary states reached at the registers are collected. Simulation stops when a new terna... |

16 | Retiming and resynthesis: A complexity perspective
- Jiang, Brayton
(Show Context)
Citation Context ...equences and functional test-vectors developed for the original design. Also, it was shown that if retiming is interleaved with CS, then proving sequential equivalence is, in general, PSPACE-complete =-=[11]-=-. Thus, sequential synthesis based on register sweeping and retiming, although scalable, has limited optimization power, invalidates state-encoding, initialization-sequences and testbenches, and may b... |

14 |
Reducing structural bias
- Chatterjee, Mishchenko, et al.
(Show Context)
Citation Context ...riting [20]. • resyn2 is a CS script that performs 10 iterations of AIG rewriting that are more diverse than those of resyn. • choice is a CS script that allows for accumulation of structural choices =-=[6]-=-; choice runs resyn followed by resyn2 and collects three snapshots of the network: the original, the final, and the intermediate one saved after resyn. • if is a structural FPGA mapper with priority ... |

14 | Efficient Latch Optimization Using Exclusive Sets
- Sentovich, Toma, et al.
- 1997
(Show Context)
Citation Context ...e POs. Simple induction [10] and k-step induction [5][23][17] can be used to compute pairs of sequentially-equivalent nodes. This technique subsumes several methods to detect equivalent registers [15]=-=[26]-=-. We call this kind of synthesis, verifiable sequential synthesis (VSS) and show that it mitigates most of the drawbacks listed above for TSS. Although VSS is quite restrictive compared to TSS, it is ... |

9 |
IChecker: An efficient checker for inductive invariants
- Lu, Cheng
- 2006
(Show Context)
Citation Context ...the sequential behavior of the circuit, leading to a substantial reduction of the circuit, e.g. some pieces of logic can be discarded because they no longer affect the POs. k-step induction [9][4][21]=-=[15]-=- can be used to efficiently compute pairs of sequentially-equivalent nodes. We call this kind of synthesis, verifiable sequential synthesis (VSS) and show that it mitigates most of the drawbacks liste... |

6 |
Inductive equivalence checking under retiming and resynthesis
- Jiang, Hung
(Show Context)
Citation Context ...hat there is no further restructuring of the circuit after VSS. Otherwise, equivalent points common to both networks may be lost, resulting in the loss of the ability to prove equivalence inductively =-=[12]-=-. It is also important that when ISEC is applied to the results of VSS, retiming should be disabled (command “dsec –r”) in the verification algorithm. However, for ISEC, not specific to VSS, it was fo... |

1 |
Exact removal of redundant state registers using Binary Decision Diagrams
- Lin, Newton
(Show Context)
Citation Context ...t the POs. Simple induction [10] and k-step induction [5][23][17] can be used to compute pairs of sequentially-equivalent nodes. This technique subsumes several methods to detect equivalent registers =-=[15]-=-[26]. We call this kind of synthesis, verifiable sequential synthesis (VSS) and show that it mitigates most of the drawbacks listed above for TSS. Although VSS is quite restrictive compared to TSS, it... |