## Bounded-skew clock and steiner routing under elmore delay (1995)

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Venue: | UCLA Computer Science Department |

Citations: | 17 - 5 self |

### BibTeX

@TECHREPORT{Cong95bounded-skewclock,

author = {Jason Cong and Andrew B. Kahng and Cheng-kok Koh and C. -w. Albert Tsao},

title = {Bounded-skew clock and steiner routing under elmore delay},

institution = {UCLA Computer Science Department},

year = {1995}

}

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### Abstract

Abstract: We study the minimum-cost bounded-skew routing tree problem under the Elmore delay model. We present two approaches to construct bounded-skew routing trees: (i) the Boundary Merging and Embedding (BME) method which utilizes merging points that are restricted to theboundariesof merging regions, and (ii) the Interior Merging and Embedding (IME) algorithm which employs a sampling strategy and dynamic programming to consider merging points that are interior to, rather than on the boundary of, the merging regions. Our new algorithms allow accurate control of Elmore delay skew, and show the utility of merging points inside merging regions. 1

### Citations

97 | A new class of iterative Steiner tree heuristics with good performance - Kahng, Robins - 1992 |

85 | Zero skew clock routing with minimum wirelength
- Chao, Hsu, et al.
- 1992
(Show Context)
Citation Context ...ions. 1 Introduction Control of signal delay is important in layout synthesis of high performance systems. Recent works on clock routing have accomplished exact zero skew under the Elmore delay model =-=[17, 5, 11]-=-, and given new single-layer (planar) constructions [18, 15, 16]. A detailed review of clock tree and Steiner routing algorithms is given in [14]. In practice, circuits will operate correctly within a... |

82 |
On optimal interconnections for VLSI
- Kahng, Robins
- 1995
(Show Context)
Citation Context ...ed exact zero skew under the Elmore delay model [17, 5, 11], and given new single-layer (planar) constructions [18, 15, 16]. A detailed review of clock tree and Steiner routing algorithms is given in =-=[14]-=-. In practice, circuits will operate correctly within a given skew tolerance, and indeed “exact zero skew” is never an actual design requirement [14]. Two recent works [8, 12] have addressed the bound... |

57 |
An exact zero-skew clock routing algorithm
- Tsay
- 1993
(Show Context)
Citation Context ...ions. 1 Introduction Control of signal delay is important in layout synthesis of high performance systems. Recent works on clock routing have accomplished exact zero skew under the Elmore delay model =-=[17, 5, 11]-=-, and given new single-layer (planar) constructions [18, 15, 16]. A detailed review of clock tree and Steiner routing algorithms is given in [14]. In practice, circuits will operate correctly within a... |

55 | Zero-Skew Clock Routing Trees With Minimum Wirelength
- Boese, Kahng
- 1992
(Show Context)
Citation Context ...l routing algorithms that construct BSTs under the linear, i.e., pathlength, delay model. The enabling concept in [8, 12] is that of a merging region, which generalizes the merging segment concept of =-=[1, 4, 10]-=- for zeroskew clock trees. 7000 6500 3 6000 3 5500 HSPICE 50003 3 Skew 4500 (ps) 40003 3 3500 3 3 3000 2500 3 2000 0 50 100 150 200 250 Pathlength Skew (µm) (a) HSPICE Skew (ps) 600 500 400 300 200 3 ... |

54 | Nearoptimal critical sink routing tree constructions
- Boese, Kahng, et al.
- 1995
(Show Context)
Citation Context ...BST solutions of [8, 12] are simply unable to meet tight skew bounds (of 100ps or less). On the other hand, Figure 1(b) demonstrates the accuracy and fidelity of Elmore delay skew to actual skew; cf. =-=[2]-=-. Converting a zero pathlength skewrouting into a zero Elmore delay skewrouting via the use of “snaking” [17] usually entails substantial increase in total wirelength. Thus, in this work, we pursue ne... |

53 | Zero skew clock net routing - Chao, Hsu, et al. - 1992 |

50 | A clustering-based optimization algorithm in zero-skew routings
- Edahiro
- 1993
(Show Context)
Citation Context ...ions. 1 Introduction Control of signal delay is important in layout synthesis of high performance systems. Recent works on clock routing have accomplished exact zero skew under the Elmore delay model =-=[17, 5, 11]-=-, and given new single-layer (planar) constructions [18, 15, 16]. A detailed review of clock tree and Steiner routing algorithms is given in [14]. In practice, circuits will operate correctly within a... |

28 |
Optimal wiresizing under Elmore delay model
- Cong, Leung
- 1995
(Show Context)
Citation Context ...include well-behaved sampling segments other than Manhattan arcs. We also plan to combine the techniques of BST topology generation with our recent work on optimal sizing of interconnects and drivers =-=[7, 9]-=-, and develop a practical clock routing algorithm which carries out simultaneous topology generation, buffer insertion, and wiresizing to achieve bounded skew with minimum power dissipation under vari... |

22 |
Minimum path-length equi-distant routing
- Edahiro
- 1992
(Show Context)
Citation Context ...l routing algorithms that construct BSTs under the linear, i.e., pathlength, delay model. The enabling concept in [8, 12] is that of a merging region, which generalizes the merging segment concept of =-=[1, 4, 10]-=- for zeroskew clock trees. 7000 6500 3 6000 3 5500 HSPICE 50003 3 Skew 4500 (ps) 40003 3 3500 3 3 3000 2500 3 2000 0 50 100 150 200 250 Pathlength Skew (µm) (a) HSPICE Skew (ps) 600 500 400 300 200 3 ... |

20 | Minimum-cost bounded-skew clock routing”, Proc
- Cong, Koh
- 1995
(Show Context)
Citation Context ...ting algorithms is given in [14]. In practice, circuits will operate correctly within a given skew tolerance, and indeed “exact zero skew” is never an actual design requirement [14]. Two recent works =-=[8, 12]-=- have addressed the bounded-skew routing tree (BST) problem, and proposed clock and Steiner global routing algorithms that construct BSTs under the linear, i.e., pathlength, delay model. The enabling ... |

15 | Perfect-balance Planar Clock Routing with Minimal Path-length
- Zhu, Dai
- 1992
(Show Context)
Citation Context ...yout synthesis of high performance systems. Recent works on clock routing have accomplished exact zero skew under the Elmore delay model [17, 5, 11], and given new single-layer (planar) constructions =-=[18, 15, 16]-=-. A detailed review of clock tree and Steiner routing algorithms is given in [14]. In practice, circuits will operate correctly within a given skew tolerance, and indeed “exact zero skew” is never an ... |

11 | Planar-dme: Improved planar zero-skew clock routing with minimum pathlength delay,” in Proc. European Design Automation Conf. with with EUROVHDL
- Kahng, Tsao
- 1994
(Show Context)
Citation Context ...yout synthesis of high performance systems. Recent works on clock routing have accomplished exact zero skew under the Elmore delay model [17, 5, 11], and given new single-layer (planar) constructions =-=[18, 15, 16]-=-. A detailed review of clock tree and Steiner routing algorithms is given in [14]. In practice, circuits will operate correctly within a given skew tolerance, and indeed “exact zero skew” is never an ... |

10 | Low-cost single-layer clock trees with exact zero Elmore delay skew
- Kahng, Tsao
- 1994
(Show Context)
Citation Context ...yout synthesis of high performance systems. Recent works on clock routing have accomplished exact zero skew under the Elmore delay model [17, 5, 11], and given new single-layer (planar) constructions =-=[18, 15, 16]-=-. A detailed review of clock tree and Steiner routing algorithms is given in [14]. In practice, circuits will operate correctly within a given skew tolerance, and indeed “exact zero skew” is never an ... |

7 | High-Performance Routing Trees - Boese, Kahng, et al. - 1993 |

6 | On the bounded-skew routing tree problem - HUANG, KAHNG, et al. - 1995 |

5 |
An edge-based heuristic for rectilinear steiner trees
- Borah, Owens, et al.
- 1994
(Show Context)
Citation Context ...s (after re-rooting) become closer without much change in the subtree costs. As a result, this version of ExG-DME also very closely matches one of the best known heuristics for unbounded-skew routing =-=[3]-=-. The work of [12] also gives an Extended-Planar-DME method which again matches the best known heuristics [15] when the routing tree must be embeddable on a single layer. t min(p) skew(p) = t b a max(... |

4 |
SimultaneousDriver and Wire Sizing for Performance and
- Cong, Koh
- 1994
(Show Context)
Citation Context ...include well-behaved sampling segments other than Manhattan arcs. We also plan to combine the techniques of BST topology generation with our recent work on optimal sizing of interconnects and drivers =-=[7, 9]-=-, and develop a practical clock routing algorithm which carries out simultaneous topology generation, buffer insertion, and wiresizing to achieve bounded skew with minimum power dissipation under vari... |

3 | Simultaneous Driver and Wire Sizing for Performanceand Power Optimization - Cong, Koh - 1994 |

1 |
Perfect-Balance Planar Clock Routing with
- Zhu, Dai
(Show Context)
Citation Context |

1 |
Near-OptimalCritical Sink Routing Tree Constructions
- Boese, Kahng, et al.
- 1995
(Show Context)
Citation Context ...BST solutions of [8, 12] are simply unable to meet tight skew bounds (of 100ps or less). On the other hand, Figure 1(b) demonstrates the accuracy and fidelity of Elmore delay skew to actual skew; cf. =-=[2]-=-. Converting a zero pathlength skewrouting into a zero Elmore delay skewrouting via the use of “snaking” [17] usually entails substantial increase in total wirelength. Thus, in this work, we pursue ne... |