Interconnect Design Using Convex Optimization (1994)
| Venue: | In Proc. IEEE Custom Integrated Circuits Conf |
| Citations: | 5 - 0 self |
BibTeX
@INPROCEEDINGS{Sancheti94interconnectdesign,
author = {Piyush K. Sancheti and Sachin S. Sapatnekar},
title = {Interconnect Design Using Convex Optimization},
booktitle = {In Proc. IEEE Custom Integrated Circuits Conf},
year = {1994},
pages = {549--552}
}
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Abstract
Two wire sizing formulations for optimizing interconnect are presented. The first minimizes the delay under wire width constraints, while the second minimizes the wiring area under delay and width constraints. A convex programming formulation is proposed, and an efficient algorithm is used to perform the optimization. Experimental results show that the first formulation, which has been the prevalent one in the literature, provides bad engineering solutions, and that the second formulation leads to significantly better results.
Citations
| 111 | A new algorithm for minimizing convex functions over convex sets - Vaidya - 1996 |
| 81 | An exact solution to the transistor sizing problem for cmos circuits using convex optimization - Sapatnekar, Rao, et al. - 1993 |
| 62 | Performance-Driven Interconnect Design Based on Distributed RC Delay Model - Cong, Leung, et al. - 1993 |
| 48 | Optimal wiresizing under the distributed Elmore delay model - Cong, Leung - 1995 |
| 41 | RC interconnect optimization under the Elmore delay model - Sapatnekar - 1994 |
| 37 | Geometric programming: methods, computations and applications - Ecker - 1980 |
| 10 | Signal delay inRC tree networks - Rubenstein, eld, et al. - 1983 |
