Optimization of Phase-Locked Loop Circuits via Geometric Programming (2003)
| Venue: | In Proceedings of the Custom Integrated Circuits Conference (CICC |
| Citations: | 6 - 3 self |
BibTeX
@INPROCEEDINGS{Colleran03optimizationof,
author = {David M. Colleran and Clemenz Portmann and Arash Hassibi and Cesar Crusius and Sunderarajan S. Mohan and Stephen Boyd and Thomas H. Lee and Maria del Mar Hershenson},
title = {Optimization of Phase-Locked Loop Circuits via Geometric Programming},
booktitle = {In Proceedings of the Custom Integrated Circuits Conference (CICC},
year = {2003},
pages = {377--380}
}
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Abstract
We describe the global optimization of phaselocked loop (PLL) circuits using geometric programming (GP). Equations for the jitter, frequency range, and power of the PLL are presented in GP form. An array of PLL circuits was automatically generated using this technique in a########### ### ### CMOS process. Silicon measurements show good agreement with the model. The results include a PLL with a period jitter of RMS and an accumulated jitter of RMS, consuming .
Citations
| 2134 | Convex Optimization - Boyd, Vandenberghe - 2004 |
| 40 | Jitter in ring oscillators - McNeill - 1994 |
| 36 | Geometric programming: theory and application - Duffin, Peterson, et al. - 1967 |
| 31 | The Design of Low Noise Oscillators - Hajimiri, Lee - 1999 |
| 22 | GPCAD: A tool for CMOS op-amp synthesis - Hershenson, Boyd, et al. - 1998 |
| 13 | Jitter optimization based on phaselock loop design parameters - Mansuri, Yang |
| 8 | A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation - Kaenel, Aebischer, et al. - 1996 |
